



System Controller: PCI Bus Control Signals
PCI Interface Registers
PCI0 and PCI1 contain the same set of internal registers, but are located at different offsets. A CPU access to the MV64460 PCIx Configuration register is performed via the PCIx Config- uration Address and Data registers. Only PCI0 is functional on the PmPPC7448.
All PCI configuration registers are located at their standard offset in the configuration header, as defined in the PCI specification, when accessed from their corresponding PCI bus. For example, if a master on PCI0 performs a PCI configuration cycle on PCI’s Status and Command register, the register is located at 0x004.
The PmPPC7448 module may generate interrupts to other PCI devices by accessing door-
PCI BUS CONTROL SIGNALS
The following signals for the PCI interface are available on connectors P11, P12, and P13. Refer to the PCI specification for details on using these signals. All signals are
Note: The PmPPC7448 host board must adhere to the PCI Local Bus Specification (Revision 2.3) for terminating
JTAG signals.
ACK64*: ACKNOWLEDGE | This sustained | |
| willing to transfer data using 64 bits. | |
AD[31:00]: | ADDRESS and DATA bus (bits | |
| and data handling. A bus transaction consists of an address phase followed by one or more | |
| data phases. |
|
AD[63:32]: | ADDRESS and DATA bus (bits | |
| phase the upper | |
| reserved. During a data phase, an additional | |
| transaction has been negotiated by the assertion of REQ64* and ACK64*. | |
C/BE[3:0]*: | BUS COMMAND and BYTE ENABLES | These |
depending on the phase of a transaction. During the address phase of a transaction these lines define the bus command. During a data phase the lines are used as byte enables.
PmPPC7448 User’s Manual |