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Emerson PMPPC7448 user manual CPLD:Reset Registers

Models: PMPPC7448

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PCI Reset Out Enable Register (ROER)

The Reset Out Enable register determines the functionality of the PCI ResetOut signal.

CPLD:Reset Registers

SCL

SDA

I2C

SCL:	Serial I2C Clock
	1	Tri-states the PLD
	0	Drives logic low
SDA: Serial I2C Data/Address
	1	Tri-states the PLD
	0	Drives logic low
R:	Reserved (default is 00)
I2C:	I2C reset
	1	Causes the I2C bus to be reset into a known state
	0	No I2C reset (default)
FR:	Flash Reset command
	1	Causes Flash to be reset
	0	No Flash reset (default)
SR:	Soft Reset command
	1	Causes a soft reset to the CPU and resets on-board Flash
	0	No soft reset (default)
HR: Hard Reset command
	1	Causes a hard reset on board
	0	No hard reset (default)

COPH

PCI0

R:Reserved (default is 00)

7-2

PmPPC7448 User’s Manual

10006757-02

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Emerson PMPPC7448 user manual CPLD:Reset Registers

Contents

PmPPC7448: PowerPC-BasedProcessor PMC Module User’s ManualDate Revision LevelPrincipal Changes EMC COMPLIANCE Regulatory Agency Warnings & NoticesFCC RULES AND REGULATIONS — PART Product Regulatory Agency Warnings & NoticescontinuedManufacturer’s Name Model Name/Number4On-CardMemory Configuration Contents2 Setup 1 Overview9 Real-TimeClock Contentscontinued8 Serial Input/Output 10Development Mezzanine Card12 Acronyms Contentscontinued10006757-02 blank pagePmPPC7448 User’s Manual Figures PmPPC7448 User’s Manual blank pageviii 10006757-02Tables 10006757-02 blank pagePmPPC7448 User’s Manual Registers 10006757-02 blank pagePmPPC7448 User’s Manual Section COMPONENTS AND FEATURESOverview System Controller/PCI BridgeOverview: Components and Features Development Mezzanine Card DMCFront Panel Overview: Functional OverviewFUNCTIONAL OVERVIEW Development Mezzanine Card DMCHex Address Overview: Physical Memory MapPHYSICAL MEMORY MAP MemoryAddress AccessHex Physical ModeADDITIONAL INFORMATION SpecificationOverview: Additional Information Product CertificationOverview: Additional Information UL CertificationSpecification TypeTechnical References RoHS ComplianceTerminology and Notation Device / InterfaceDocument: continuedOverview: Additional Information Device / InterfacePmPPC7448 User’s Manual blank page1-10 10006757-02PMPPC7448 CIRCUIT BOARD SetupELECTROSTATIC DISCHARGE WidthSetup: PmPPC7448 Circuit Board C279 Setup: PmPPC7448 Circuit BoardConnectors Setup: PmPPC7448 Circuit BoardLEDs Setup: PmPPC7448 Circuit BoardEthernet Reset SW1Front Panel SerialSetup: PmPPC7448 Circuit Board Resetthe switch Setup: PmPPC7448 Setup PMPPC7448 SETUPEnvironmental Considerations Power RequirementsWatt Requirements/Configuration risk of damage to the boardPmPPC7448PmPPC7448 BottomsideBottomside Installing the ModuleSetup: PmPPC7448 Setup baseboard Setup: TroubleshootingTROUBLESHOOTING Technical Support Setup: TroubleshootingSerial Number Product RepairSetup: Troubleshooting Product ID8310 Excelsior Drive Madison, WI Emerson Network Power, Embedded ComputingTest and Repair Services Department RMA #____________Category MPC7448 Key FeaturesCentral Processing Unit SectionPROCESSOR INITIALIZATION PROCESSOR RESETDefault After Initialization Hex RegisterCentral Processing Unit:Processor Initialization Hardware Implementation Dependent 0 RegisterXAE: Extended Addressing Enabled Central Processing Unit:Processor InitializationHID1ECLK HRESETHardware Implementation Dependent 1 Register HID1BCLKHRESET Central Processing Unit:Exception HandlingEXCEPTION HANDLING HID1ECLKPriority Instruction Dispatch/ExecutionPost-InstructionExecution ExceptionMachine State Register Central Processing Unit:Exception ProcessingEXCEPTION PROCESSING Notes: continuedFP Exception Mode Central Processing Unit:Exception ProcessingFP Exception Mode: continued Central Processing Unit:Cache MemoryCACHE MEMORY L1 Cache L2 Cache Central Processing Unit:Cache MemoryL2HWF: L2 Hardware Flush 0Flush disabled Central Processing Unit:Cache MemoryDefault Configuration On-CardMemory ConfigurationBOOT MEMORY CONFIGURATION USER FLASHNVRAM ALLOCATION On-CardMemory Configuration:On-CardSDRAMON-CARDSDRAM Address Offset hex On-CardMemory Configuration:NVRAM AllocationWindow Size Name10006757-02 blank pagePmPPC7448 User’s Manual System Controller SectionCPU Interface Registers System Controller: CPU InterfaceCPU INTERFACE MEMORY INTERFACE DDR SDRAM ControllerDEVICE CONTROLLER INTERFACE System Controller: Device Controller InterfaceInternal SRAM Device Control Registers Timer/CounterSystem Controller: Internal IDMA Controller INTERNAL IDMA CONTROLLERPCI Subsystem Device and Vendor ID Assignment PCI Configuration SpaceSystem Controller: PCI Interface PCI Read/WriteMax SDRAM Size System Controller: PCI InterfaceSDRAM Size SDRAM SizePCI Interface Registers System Controller: PCI Bus Control SignalsPCI BUS CONTROL SIGNALS AD31:00GNT*: GRANT C/BE7:4EREADY: READY INTA*, INTB*, INTC*, INTDSERR RESET_OUT*: RESET OUTPUTPRESENT*: PRESENT STOP*: STOPP11 Signal System Controller: PMC Connector PinoutsPMC CONNECTOR PINOUTS P12 SignalP13 and P14 Pin Assignments P13 SignalP14 Signal System Controller: PMC Connector PinoutsP13 Signal PMC ConnectorSystem Controller: PMC Connector Pinouts P14 SignalOutbound Doorbells System Controller: DoorbellRegistersDOORBELL REGISTERS Inbound DoorbellsSystem Controller: 66 MHz Bus Operation WATCHDOG TIMERRESET 66 MHZ BUS OPERATIONSection Ethernet InterfaceMV64460 ETHERNET REGISTERS ETHERNET CONNECTION P1 Ethernet Interface: Ethernet AddressETHERNET ADDRESS 00 80 F9 xx yy zzcable may result in a disconnection SignalEthernet Interface: Ethernet Connection P1 Mini-BUSB Pin10006757-02 blank pagePmPPC7448 User’s Manual Reset Command Register RCR RESET REGISTERSReset Event Register RER CPLDCPLD:Reset Registers CPLD:Interrupt Registers INTERRUPT REGISTERSCPLD:Interrupt Registers Interrupt Enable Register IERInterrupt Pending Register IPR EREADY REGISTER ERDY CPLD:Product ID Register PIRPRODUCT ID REGISTER PIR REVISION REGISTERSHardware Version Register HVR CPLD:Board Configuration RegistersBOARD CONFIGURATION REGISTERS PLD Version Register PVRCPLD:Board Configuration Registers 0 DMC is not installed10006757-02 blank pagePmPPC7448 User’s Manual Serial Input/Output BRGx Configuration RegisterMPSCx Main Configuration Registers MULTI-PROTOCOLSERIAL CONTROLLERS MPSCI2C INTERFACE BRGx Tuning RegisterSerial Input/Output: I2C Interface I/O CONNECTIONDescription:2 Serial Input/Output: I/O ConnectionMini-USBPin DB9 Pin10006757-02 blank pagePmPPC7448 User’s Manual OPERATION BLOCK DIAGRAMReal-TimeClock SectionData Real-TimeClock: Clock OperationCLOCK OPERATION Function/RangeReal-TimeClock: Clock Operation ST: Stop bit 1=Stops the oscillator10006757-02 blank pagePmPPC7448 User’s Manual Section Development Mezzanine CardDMC CIRCUIT BOARD WidthDevelopment Mezzanine Card:DMC Circuit Board Serial NumbersP1 Connector Pin Assignments Development Mezzanine Card:ConnectorsCONNECTORS SignalSignal Development Mezzanine Card:ConnectorsSignal 3.3V: 3.3 V is the power supply to the DMC analogDMC_OE WE0 LA17:2 BADDR2:0 AD7:0 FILT_TX FILT_RX CPU_VIO MPC7448_TCK DMC_BOOT_SRC DMC_JP4:3,1MPC7448_TMS DEBUG_SRESET DEBUG_HRESET LED4:1 MPC7448_TDO MPC7448_TDI DEBUG_TRSTSignal P2 EIA-232InterfaceDevelopment Mezzanine Card:Connectors SignalP3 JTAG/COP Development Mezzanine Card:PmPPC7448 to DMC JTAGPMPPC7448 TO DMC JTAG MPC7448HRESETSignal P4 JTAG Chain HeaderSignal Development Mezzanine Card:PmPPC7448 to DMC JTAGSignal Development Mezzanine Card:DMC Jumpers JP1DMC JUMPERS JP1 SignalDEBUG/STATUS LEDS Jumper Setting RegisterDevelopment Mezzanine Card:Debug/Status LEDs Installing the DMC Card Development Mezzanine Card:DMC SetupDMC SETUP DMC Location on PmPPC7448 Development Mezzanine Card:DMC SetupFigure RJ45Technical Support Development Mezzanine Card:TroubleshootingTROUBLESHOOTING Product RepairTest and Repair Services Department Emerson Network PowerDevelopment Mezzanine Card:Troubleshooting 8310 Excelsior Drive Madison, WISection COMMAND-LINEFEATURESMonitor BASIC OPERATION Power-up/ResetSequenceMonitor: Basic Operation 11-3 Monitor: Basic Operation10006757-02 baudrateMONITOR RECOVERY AND UPDATES Monitor: Monitor Recovery and UpdatesPOST Diagnostic Results Recovering the MonitorUpdating the Monitor via TFTP Monitor: Monitor Recovery and UpdatesMonitor: Monitor Recovery and Updates 4Enter showpci at the command promptResetting Environment Variables Monitor: Monitor Recovery and UpdatesMONITOR COMMAND REFERENCE Monitor: Accessing the Console Over EthernetACCESSING THE CONSOLE OVER ETHERNET Command Help Monitor: Boot CommandsCommand Syntax BOOT COMMANDSbootp bootelfbootm bootvtftpboot Monitor: Memory Commandsrarpboot MEMORY COMMANDSfind Monitor: Memory CommandsMonitor: Memory Commands erase Monitor: Flash CommandsFLASH COMMANDS flinfoprotect Monitor: EEPROM/I2C CommandsEEPROM/I2C COMMANDS eepromiprobe icrc32iloop DEFINITION: iprobeTEST COMMANDS Monitor: Environment Parameter CommandsENVIRONMENT PARAMETER COMMANDS printenvdiags Monitor: Other CommandsOTHER COMMANDS mtestecho crc32date enumpciisdram helpiminfo loopping resetDEFINITION: reset DEFINITION: ping hostscript DefaultMonitor: Environment Variables showmacMonitor: Environment Variables Description: continuedDefault VariableMonitor: Environment Variables Variable:1Default VariableBinary Monitor: TroubleshootingDOWNLOAD FORMATS Motorola S-RecordPmPPC7448 User’s Manual blank page11-26 10006757-02CPLD AcronymsASCII cPSBSROM SDRAMSO-DIMM UARTIndex Index continued terminology . . . . . . . . . . . . . . . . . . watchdog timer . . . . . . . . . . . . . .Index continued UL certifications . . . . . . . . . . . . . . .10006757-02 blank pagePmPPC7448 User’s Manual Notes E M E R S O N. C O N S I D E R I T S O L V E D