



CPLD:
Interrupt Registers 























Interrupt Enable Register (IER)
Register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved
SR0EN PR0EN
R:Reserved (default is 000)
SR0EN: PCI0 SERR Enable interrupt routed from PCI0 SERR to MV64460
1Enabled to generate an interrupt
0Disabled (default)
PR0EN: PCI0 PERR Enable interrupt routed from PCI0 PERR to MV64460
1Enabled to generate an interrupt
0Disabled (default)
Interrupt Pending Register (IPR)
This register allows software to determine which source has caused an interrupt.
Register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved
SERR0 PERR0
R:Reserved (default is 000)
SERR0: PCI0 SERR Enable
1SERR has occurred and is enabled (IER SR1EN=1)
0No SERR (default)
PERR0: PCI0 PERR Enable
1PERR has occurred and is enabled (IER PR1EN=1)
0No PERR (default)
PmPPC7448 User’s Manual |