Central Processing Unit Cache Memory | Emerson PMPPC7448 manual

Central Processing Unit:Cache Memory

L2HWF: L2 Hardware Flush

0Flush disabled

1Flush enabled

LVRAME: LVRAM enable

0LVRAM mode disabled

1LVRAM mode enabled

LVRAMM: LVRAM mode (read-only)

000Reserved if LVRAM mode is enabled

001Mode 1

010Mode 2

011Mode 3

100Mode 4

101Mode 5

110Mode 6

111Mode 7

The L2 cache is cleared following a power-on or hard reset. Before enabling the L2 cache, configuration parameters must be set in the L2CR and the L2 tags must be globally invali- dated. Initialize the L2 cache during system start-up per the following sequence:

1Power-on reset (automatically performed by the assertion of HRESET* signal).

2Disable interrupts and dynamic power management (DPM).

3Disable L2 cache by clearing L2CR[L2E].

4Perform an L2 global invalidate.

5Enable the L2 cache for normal operation by setting the L2CR[L2E] bit to 1.

3-12

PmPPC7448 User’s Manual

10006757-02

Image 50

Emerson PMPPC7448 user manual Central Processing Unit Cache Memory

Contents

PmPPC7448 PowerPC-Based Processor PMC Module Revision Level Principal Changes Date EMC Compliance Regulatory Agency Warnings & NoticesFCC Rules and Regulations Part Model Name/Number Manufacturer’s NameProduct Contents Contents Acronyms Blank Figures Viii Tables Blank Registers Xii Components and Features Overview Overview Components and Features Development Mezzanine Card DMC Overview Functional Overview Functional Overview Overview Physical Memory Map Physical Memory MAP Hex Physical Access Address Mode Description See EBFF,FFFF Additional Information Type SpecificationOverview Additional Information Product Certification UL Certification EMC Technical References RoHS ComplianceTerminology and Notation Device / Interface Document Intel StrataFlash Embedded Memory P30 Datasheet Document Device / Interface Blank PMPPC7448 Circuit Board SetupElectrostatic Discharge Width Depth Height top side Height bottom side Setup PmPPC7448 Circuit Board C325 PLD Connectors P14 LEDs 3LED Locations, Bottom Front Panel Front Panel Reset Switch Setup PmPPC7448 Setup PMPPC7448 Setup Risk of damage to the board Power RequirementsEnvironmental Considerations Environment Range Relative Humidity Installing the Module PMC Baseboard Setup TroubleshootingTroubleshooting Technical Support Product Repair 8Serial Number and Product ID on Bottom Side Setup Troubleshooting Category MPC7448 Key Features Central Processing Unit Processor Initialization Processor ResetRegister Default After Initialization Hex Central Processing Unit Processor Initialization Hardware Implementation Dependent 0 Register Central Processing Unit Processor Initialization Hardware Implementation Dependent 1 Register Central Processing Unit Exception Handling Exception Handling Post-Instruction Execution Priority Exception Machine State Register Central Processing Unit Exception ProcessingException Processing FE0 FE1 FP Exception Mode L1 Cache Central Processing Unit Cache MemoryCache Memory L2 Cache Central Processing Unit Cache Memory Jumper Function Options Default Configuration On-Card Memory ConfigurationBoot Memory Configuration User Flash Nvram Allocation On-Card Memory Configuration On-Card SdramON-CARD Sdram Address Offset hex Name Bytes On-Card Memory Configuration Nvram AllocationWindow Size Blank System Controller XOR CPU Interface Registers System Controller CPU InterfaceCPU Interface Memory Interface Device Controller Interface System Controller Device Controller InterfaceInternal Sram Device Control Registers Timer/CounterSystem Controller Internal Idma Controller Internal Idma Controller PCI Subsystem Device and Vendor ID Assignment PCI Configuration SpaceSystem Controller PCI Interface PCI Read/Write Sdram Size PCI Interface Registers System Controller PCI Bus Control SignalsPCI BUS Control Signals Eready Ready PRESENT* Present Pin P11 Signal P12 Signal System Controller PMC Connector PinoutsPMC Connector Pinouts P11 and P12 Pin Assignments Pin P13 Signal P14 Signal P13 and P14 Pin Assignments PMC Connector 6PMC Connector Outbound Doorbells System Controller Doorbell RegistersDoorbell Registers Inbound Doorbells System Controller 66 MHz Bus Operation Watchdog TimerReset MHZ BUS Operation Ethernet Interface MV64460 Ethernet Registers Ethernet Connection P1 Ethernet Interface Ethernet AddressEthernet Address Cable may result in a disconnection Pin SignalEthernet Interface Ethernet Connection P1 Mini-B USB Pin Description RJ45 Pin Blank Reset Command Register RCR Reset RegistersReset Event Register RER Cpld Cpld Reset Registers SCL Cpld Interrupt Registers Interrupt Registers Interrupt Enable Register IER Interrupt Pending Register IPR Eready Register Erdy Cpld Product ID Register PIRProduct ID Register PIR Revision Registers Hardware Version Register HVR Cpld Board Configuration RegistersBoard Configuration Registers PLD Version Register PVR Reserved Boot Blank MULTI-PROTOCOL Serial Controllers Mpsc BRGx Configuration RegisterSerial Input/Output Serial DMA Sdma Channels I2C Interface BRGx Tuning RegisterSerial Input/Output I2C Interface Connection Serial Input/Output I/O Connection Mini-USB Pin Description DB9 Pin Blank Operation Block DiagramReal-Time Clock Address Data Function/Range Real-Time Clock Clock OperationClock Operation Don’t care bit Blank Development Mezzanine Card DMC Circuit Board Development Mezzanine Card DMC Circuit Board Serial Numbers P1 Connector Pin Assignments Development Mezzanine Card ConnectorsConnectors OUT Dmcoe 3DMC P2 Mini-USB Connector P2 EIA-232 Interface P3 JTAG/COP Development Mezzanine Card PmPPC7448 to DMC JtagPMPPC7448 to DMC Jtag P4 Jtag Chain Header 6DMC P4 Jtag Chain Header Development Mezzanine Card DMC Jumpers JP1 DMC Jumpers JP1 DEBUG/STATUS Leds Jumper Setting RegisterDevelopment Mezzanine Card Debug/Status LEDs Installing the DMC Card Development Mezzanine Card DMC SetupDMC Setup DMC Location on PmPPC7448 Development Mezzanine Card Troubleshooting 10-14 COMMAND-LINE Features Monitor Basic Operation Power-up/Reset SequenceMonitor Basic Operation 2Power-up/Reset Sequence Flowchart Monitor Recovery and Updates Monitor Monitor Recovery and UpdatesPost Diagnostic Results Recovering the Monitor Updating the Monitor via Tftp Restoring the PmPPC7448 Monitor Using the KatanaQP PCI1 Resetting Environment Variables Verify that the checksum is correct Monitor Command Reference Monitor Accessing the Console Over EthernetAccessing the Console Over Ethernet Monitor Boot Commands Boot Commands Bootp BootelfBootm Bootv Monitor Memory Commands Memory Commands Find Definition mm .b, .w, .l address Erase Monitor Flash CommandsFlash Commands Flinfo Protect Monitor EEPROM/I2C CommandsEEPROM/I2C Commands Eeprom Imd Icrc32Iloop Imm Test Commands Monitor Environment Parameter CommandsEnvironment Parameter Commands Monitor Other Commands Other Commands Echo Crc32Date Enumpci Isdram HelpIminfo Loop Run PciPing Monitor Environment Variables Environment Variables Bootfile Variable Description Binary Monitor TroubleshootingDownload Formats Motorola S-Record 11-26 GbE AcronymsCPSB PrPMC RMA Contents, table Cpld registers -1 to Index Index 11-17 UL certifications Blank 10006757-02 E R S O N. C O N S I D E R I T S O L V E D