Cpld Interrupt Registers | Emerson PMPPC7448 manual

CPLD:Interrupt Registers

SW: Software

PCI reset driven when on-board hard reset is caused by a write to the Reset Command regis- ter.

1Enabled

0Disabled

WD: WatchDog

PCI reset driven when on-board reset is caused by a timeout of the WatchDog timer.

1Enabled

0Disabled

COPH: Hard RESET

PCI reset driven when reset is caused by a COP HRESET.

1Enabled

0Disabled

PCI0: PCI reset driven when on-board reset is caused by the assertion of PCI0 reset (PCI RESET).

1Enabled

0Disabled

FP: Front Panel

PCI reset driven when on-board reset is caused by the front panel pushbutton.

1Enabled

0Disabled

INTERRUPT REGISTERS

The system error and parity error interrupts are routed to the CPLD. These signals, per the PCI specification, are sampled on the rising edge of the PCI clock. Since the PCI clock is restricted to one load, SERR and PERR from the PPMC site are sampled with a 66 MHz on- board clock. These signals should be held low for a clock cycle or they will be ignored. The following signals are routed to the appropriate MV64460 MPP pin:

•PERR and SERR are combined into a single interrupt and routed to MPP13.

•The non-maskable watchdog timer is routed to MPP18.

To control the routing of the interrupts, the CPLD implements the following enable and pending registers.

10006757-02

PmPPC7448 User’s Manual

7-3

Image 75

Emerson PMPPC7448 user manual Cpld Interrupt Registers

Contents

PmPPC7448 PowerPC-Based Processor PMC Module Revision Level Principal Changes Date Regulatory Agency Warnings & Notices FCC Rules and Regulations PartEMC Compliance Manufacturer’s Name ProductModel Name/Number Contents Contents Acronyms Blank Figures Viii Tables Blank Registers Xii Overview Components and Features Development Mezzanine Card DMC Overview Components and Features Functional Overview Overview Functional Overview Physical Memory MAP Overview Physical Memory Map EBFF,FFFF Hex Physical Access Address Mode Description See Product Certification Type SpecificationOverview Additional Information Additional Information EMC UL Certification Device / Interface Document RoHS ComplianceTerminology and Notation Technical References Document Device / Interface Intel StrataFlash Embedded Memory P30 Datasheet Blank Width Depth Height top side Height bottom side SetupElectrostatic Discharge PMPPC7448 Circuit Board C325 Setup PmPPC7448 Circuit Board PLD P14 Connectors 3LED Locations, Bottom LEDs Front Panel Front Panel Switch Reset PMPPC7448 Setup Setup PmPPC7448 Setup Environment Range Relative Humidity Power RequirementsEnvironmental Considerations Risk of damage to the board PMC Installing the Module Setup Troubleshooting TroubleshootingBaseboard Technical Support 8Serial Number and Product ID on Bottom Side Product Repair Setup Troubleshooting Central Processing Unit Category MPC7448 Key Features Processor Reset Register Default After Initialization HexProcessor Initialization Hardware Implementation Dependent 0 Register Central Processing Unit Processor Initialization Central Processing Unit Processor Initialization Hardware Implementation Dependent 1 Register Exception Handling Central Processing Unit Exception Handling Priority Exception Post-Instruction Execution Central Processing Unit Exception Processing Exception ProcessingMachine State Register FE0 FE1 FP Exception Mode Central Processing Unit Cache Memory Cache MemoryL1 Cache L2 Cache Central Processing Unit Cache Memory User Flash On-Card Memory ConfigurationBoot Memory Configuration Jumper Function Options Default Configuration On-Card Memory Configuration On-Card Sdram ON-CARD SdramNvram Allocation On-Card Memory Configuration Nvram Allocation Window SizeAddress Offset hex Name Bytes Blank XOR System Controller Memory Interface System Controller CPU InterfaceCPU Interface CPU Interface Registers System Controller Device Controller Interface Internal SramDevice Controller Interface Internal Idma Controller Timer/CounterSystem Controller Internal Idma Controller Device Control Registers PCI Read/Write PCI Configuration SpaceSystem Controller PCI Interface PCI Subsystem Device and Vendor ID Assignment Sdram Size System Controller PCI Bus Control Signals PCI BUS Control SignalsPCI Interface Registers Eready Ready PRESENT* Present P11 and P12 Pin Assignments System Controller PMC Connector PinoutsPMC Connector Pinouts Pin P11 Signal P12 Signal P13 and P14 Pin Assignments Pin P13 Signal P14 Signal 6PMC Connector PMC Connector Inbound Doorbells System Controller Doorbell RegistersDoorbell Registers Outbound Doorbells MHZ BUS Operation Watchdog TimerReset System Controller 66 MHz Bus Operation MV64460 Ethernet Registers Ethernet Interface Ethernet Interface Ethernet Address Ethernet AddressEthernet Connection P1 Mini-B USB Pin Description RJ45 Pin Pin SignalEthernet Interface Ethernet Connection P1 Cable may result in a disconnection Blank Cpld Reset RegistersReset Event Register RER Reset Command Register RCR SCL Cpld Reset Registers Interrupt Registers Cpld Interrupt Registers Interrupt Pending Register IPR Interrupt Enable Register IER Revision Registers Cpld Product ID Register PIRProduct ID Register PIR Eready Register Erdy PLD Version Register PVR Cpld Board Configuration RegistersBoard Configuration Registers Hardware Version Register HVR Reserved Boot Blank Serial DMA Sdma Channels BRGx Configuration RegisterSerial Input/Output MULTI-PROTOCOL Serial Controllers Mpsc Connection BRGx Tuning RegisterSerial Input/Output I2C Interface I2C Interface Mini-USB Pin Description DB9 Pin Serial Input/Output I/O Connection Blank Block Diagram Real-Time ClockOperation Real-Time Clock Clock Operation Clock OperationAddress Data Function/Range Don’t care bit Blank DMC Circuit Board Development Mezzanine Card Serial Numbers Development Mezzanine Card DMC Circuit Board Development Mezzanine Card Connectors ConnectorsP1 Connector Pin Assignments OUT Dmcoe P2 EIA-232 Interface 3DMC P2 Mini-USB Connector Development Mezzanine Card PmPPC7448 to DMC Jtag PMPPC7448 to DMC JtagP3 JTAG/COP 6DMC P4 Jtag Chain Header P4 Jtag Chain Header DMC Jumpers JP1 Development Mezzanine Card DMC Jumpers JP1 Jumper Setting Register Development Mezzanine Card Debug/Status LEDsDEBUG/STATUS Leds Development Mezzanine Card DMC Setup DMC SetupInstalling the DMC Card DMC Location on PmPPC7448 Development Mezzanine Card Troubleshooting 10-14 Monitor COMMAND-LINE Features Power-up/Reset Sequence Monitor Basic OperationBasic Operation 2Power-up/Reset Sequence Flowchart Recovering the Monitor Monitor Monitor Recovery and UpdatesPost Diagnostic Results Monitor Recovery and Updates Updating the Monitor via Tftp PCI1 Restoring the PmPPC7448 Monitor Using the KatanaQP Verify that the checksum is correct Resetting Environment Variables Monitor Accessing the Console Over Ethernet Accessing the Console Over EthernetMonitor Command Reference Boot Commands Monitor Boot Commands Bootv BootelfBootm Bootp Memory Commands Monitor Memory Commands Find Definition mm .b, .w, .l address Flinfo Monitor Flash CommandsFlash Commands Erase Eeprom Monitor EEPROM/I2C CommandsEEPROM/I2C Commands Protect Imm Icrc32Iloop Imd Monitor Environment Parameter Commands Environment Parameter CommandsTest Commands Other Commands Monitor Other Commands Enumpci Crc32Date Echo Loop HelpIminfo Isdram Pci PingRun Environment Variables Monitor Environment Variables Bootfile Variable Description Motorola S-Record Monitor TroubleshootingDownload Formats Binary 11-26 PrPMC AcronymsCPSB GbE RMA Index Contents, table Cpld registers -1 to 11-17 Index UL certifications Blank 10006757-02 E R S O N. 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