
Section 3



Central Processing Unit
This chapter is an overview of the processor logic on the PmPPC7448. It includes informa- tion on the CPU, exception handling, and cache memory. The PmPPC7448 utilizes the Free- scale MPC7448 RISC microprocessor, for more detailed information reference the Freescale Semiconductor MPC7450 RISC Microprocessor Family User’s Manual.
The following table outlines some of the key features for the MPC7448 CPU.
Table
Category: | MPC7448 Key Features: |
Instruction Set | Up to three instructions can be dispatched, four |
| instructions can be fetched, 12 instructions can be in |
| the queue, and 16 instructions can be at some stage of |
| execution |
|
|
CPU Speed (Internal) | Up to 1.4 GHz |
|
|
Data Bus | |
|
|
Address Bus | |
|
|
Seven Stage Pipeline | Fetch, dispatch/decode, execute, complete/write |
Control | back |
|
|
L1 Cache | 32 kilobytes instruction, 32 kilobytes data |
|
|
L2 Cache | 1 megabyte, |
| instruction and data cache, ECC capability |
|
|
Execution Units | Branch processing (BPU), four integer (IU), |
| |
| VFPU), |
| queues (FIQ, VIQ, GIQ), rename buffers, dispatch, and |
| completion |
|
|
Memory | |
Management Units |
|
|
|
Voltages | Processor core, 1.0 V at 1.0 GHz or lower, |
| 1.15 V at 1.4 GHz |
|
|
Power Management | Dynamic Frequency Switching capability |
| two and |
|
|
PmPPC7448 User’s Manual |