Emerson PMPPC7448 System Controller Doorbell Registers, Outbound Doorbells, Inbound Doorbells

System Controller: Doorbell Registers

DOORBELL REGISTERS

The MV64460 uses the doorbell registers in the messaging unit (MU) to request interrupts on both the PCI and CPU buses. There are two types of doorbell registers:

Outbound: These are set by the MV64460’s local CPU to request an interrupt service on the PCI bus.

Inbound: These are set by an external PCI agent to request interrupt service from the local CPU.

Outbound Doorbells

The local CPU generates an interrupt request to the PCI bus by setting bits in the Outbound Doorbell register (ODR). The interrupt may be masked in the Outbound Interrupt Mask reg- ister (OIMR), but that does not prevent the bit from being set in the ODR. The ODR is located at PCI_0 offset 0x1C2C.

Note: The CPU or the PCI interface can set the ODR bits. This allows for passing interrupt requests between CPU and

PCI interfaces.

Inbound Doorbells

The PCI bus generates an interrupt request to the local CPU by setting bits in the Inbound Doorbell register (IDR). The interrupt may be masked in the Inbound Interrupt Mask regis- ter (IIMR), but masking the interrupt does not prevent the bit from being set in the IDR. The IDR is located at PCI_0 offset 0x1C20.

Note: The interrupt request triggered from the PCI bus can be targeted to the CPU or to the PCI interface, depending on the software setting of the interrupt mask registers.

MONARCH FUNCTIONALITY

The PmPPC7448 can be configured to function as either a Monarch or non-Monarch mod- ule, as described in the VITA 32 PPMC specification. A Monarch is the main PPMC device on the local PCI bus. It performs enumeration on that bus after power-up and is often the inter- rupt handler. A non-Monarch module does not perform enumeration on the local bus after power-up. Bit 2 of Board Configuration Register 3 (see Register Map 7-10) at location F820,C00016 indicates how the module is configured (0=non-Monarch, 1=Monarch), as determined by the signal on pin 64 of connector P12. The software can read the Monarch line status to configure the board, and the hardware is unaffected.

The EReady register (see Register Map 7-7) at location F820,500016 has an additional bit to support Monarch functionality. EREADY bit 0 monitors the EREADY line. For a non-Mon- arch, it is presumed that this signal is initially asserted, then removed when the bus is ready for enumeration. When all the other PCI devices have stopped driving this signal low, the Monarch will enumerate the bus. Please see the PPMC standard (reference in Table 1-3) for carrier board pull-up requirements.

10006757-02 PmPPC7448 User’s Manual

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