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manual Design Guide, Intel PXA250 and PXA210 Applications Processors, February
Models:
PXA250 and PXA210
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Specs
1. Applications Processor Block Diagram
1. General Memory Interface Configuration
How to Wire
A.1 SA-1110 Hardware Migration Issues
1. Power-On Reset Timing
Boot Time Defaults
Signal Pin Descriptions
Battery Connector
Self Powered Device
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Intel
®
PXA250 and PXA210 Applications Processors
Design Guide
February, 2002
Order Number:
278523-001
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Image 1
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Contents
Intel PXA250 and PXA210 Applications Processors
Design Guide
February
Order Number
PXA250 and PXA210 Applications Processors Design Guide
Contents
Contents
USB Interface
PXA250 and PXA210 Applications Processors Design Guide
MultiMediaCard MMC
Contents
AC97
PXA250 and PXA210 Applications Processors Design Guide
Example Form Factor Reference Design Schematic Diagrams
Contents
PXA250 and PXA210 Applications Processors Design Guide
Tables
Figures
Contents
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Contents
PXA250 and PXA210 Applications Processors Design Guide
Contents
1.1 Functional Overview
Introduction
Revision History
Table 1-2. Related Documentation
1.2.1 Package Introduction
1.2 Package Information
Figure 1-1. Applications Processor Block Diagram
OS Timer
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-3. Signal Pin Descriptions Sheet 1 of
1.2.2 Signal Pin Descriptions
Introduction
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-3. Signal Pin Descriptions Sheet 2 of
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-3. Signal Pin Descriptions Sheet 3 of
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-3. Signal Pin Descriptions Sheet 4 of
PXA250 and PXA210 Applications Processors Design Guide
BOOTSEL20 Description
Table 1-3. Signal Pin Descriptions Sheet 5 of
Introduction
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-3. Signal Pin Descriptions Sheet 6 of
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-3. Signal Pin Descriptions Sheet 7 of
PXA250 and PXA210 Applications Processors Design Guide
Figure 1-2. PXA250 Applications Processor
Introduction
1-11
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Introduction
1-13
Introduction
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Figure 1-3. PXA210 Applications Processor
Introduction
1-15
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Introduction
1-17
Introduction
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Introduction
2.1 Overview
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
System Memory Interface
Figure 2-1. General Memory Interface Configuration
PXA250 and PXA210 Applications Processors Design Guide
Card Memory Interface
2.2 SDRAM Interface
2.3 SDRAM memory wiring diagram
System Memory Interface
Table 2-1. Memory Address Map
Figure 2-2. SDRAM Memory System Example
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
System Memory Interface
2.4 SDRAM Support
Table 2-2. SDRAM Memory Types Supported by the Applications Processor
PXA250 and PXA210 Applications Processors Design Guide
System Memory Interface
2.5 SDRAM Address Mapping
Table 2-3. Normal Mode Memory Address Mapping
PXA250 and PXA210 Applications Processors Design Guide
2.6.1 Overview
2.6 Static Memory
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
Table 2-5. Valid Booting Configurations Based on Package Type
2.6.2 Boot Time Defaults
Table 2-6. BOOTSEL Definitions Sheet 1 of
System Memory Interface
2.6.4 Variable Latency I/O Interface Overview
2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options
Table 2-6. BOOTSEL Definitions Sheet 2 of
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
System Memory Interface
memlk
nCS0
System Memory Interface
2.6.5 External Logic for PCMCIA Implementation
2-11
PXA250 and PXA210 Applications Processors Design Guide
System Memory Interface
PXA250 Applications Processor
Socket
2-13
System Memory Interface
PXA250
Socket
System Memory Interface
2.6.6 DMA / Companion Chip Interface
Connect a companion chip to the applications processor via
Alternate Bus Master Mode Variable Latency I/O Flow through DMA
Memory
PXA250
Controller
PXA250
System Memory Interface
PXA250
Figure 2-7. Variable Latency I/O
EXTERNAL SYSTEM
2.7.1 System Memory Topologies Min and Max Simulated Loading
2.7 System Memory Layout Guidelines
CS, CKE, DQM CLK, MA
CS, CKE, DQM CLK, MA
Table 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals
2.7.2 System Memory Recommended Trace Lengths
System Memory Interface
Figure 2-11. MD maximum loading topology
3.1 LCD Display Overview
LCD Display Controller
3.2 Passive DSTN Displays
Table 3-1. LCD Controller Data Pin Utilization Sheet 1 of
Table 3-2. Passive Display Pins Required
3.2.1 Typical Connections for Passive Panel Displays
3.2.1.1 Passive Monochrome Single Panel Displays
LCD Display Controller
3.2.1.3 Passive Monochrome Dual Panel Displays
3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data
LCD Display Controller
PXA250 and PXA210 Applications Processor Design Guide
3.2.1.5 Passive Color Dual Panel Displays
3.2.1.4 Passive Color Single Panel Displays
LCD Display Controller
Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection
LCD Display Controller
3.3 Active TFT Displays
Figure 3-5. Passive Color Dual Panel Displays Typical Connection
PXA250 and PXA210 Applications Processor Design Guide
Table 3-3. Active Display Pins Required
3.3.1 Typical connections for Active Panel Displays
LCD Display Controller
PXA250 and PXA210 Applications Processor Design Guide
LCD Display Controller
3.4 PXA250 Pinout
Figure 3-6. Active Color Display Typical Connection
Table 3-4. PXA250 LCD Controller Ball Positions Sheet 1 of
3.5 Additional Design Considerations
3.5.3 Signal Routing and Buffering
3.5.1 Contrast Voltage
3.5.2 Backlight Inverter
LCD Display Controller
3.5.4 Panel Connector
PXA250 and PXA210 Applications Processor Design Guide
PXA250 and PXA210 Applications Processor Design Guide
LCD Display Controller
4.1.1 Operation if GPIOn and GPIOx are Different Pins
4.1 Self Powered Device
USB Interface
Figure 4-1. Self Powered Device
4.1.2 Operation if GPIOn and GPIOx are the Same Pin
4.2 Bus Powered Device
USB Interface
PXA250 and PXA210 Applications Processors Design Guide
5.1.1 Signal Description
5.1 Schematics
MultiMediaCard MMC
Table 5-1. MMC Signal Description
Table 5-2. SDCard Socket Signals
5.1.2 How to Wire
MultiMediaCard MMC
Table 5-3. MMC Controller Supported Sockets and Devices
MultiMediaCard MMC
Figure 5-1. Applications Processor MMC and SDCard Signal Connections
5.1.2.2 MMC Socket
5.1.2.1 SDCard Socket
MultiMediaCard MMC
PXA250 and PXA210 Applications Processors Design Guide
MultiMediaCard MMC
5.1.3 Simplified Schematic
5.1.4 Pull-up and Pull-down
5.2 Utilized Features
MultiMediaCard MMC
Table 5-4. SDCard Pull-up and Pull-down Resistors
AC97
6.1 Schematics
Figure 6-1. AC97 connection
PXA250 and PXA210 Applications Processors Design Guide
AC97
6.2 Layout
PXA250 and PXA210 Applications Processors Design Guide
7.1.1 Signal Description
7.1 Schematics
Table 7-1. I2C Signal Description
PXA250 and PXA210 Applications Processors Design Guide
7.1.3 Other Uses of I2C
7.1.2 Digital-to-Analog Converter DAC
Figure 7-1. Linear Technology DAC with I2C Interface
PXA250 and PXA210 Applications Processors Design Guide
Figure 7-2. Using an Analog Switch to Allow a Second CF Card
7.1.4 Pull-Ups and Pull-Downs
Figure 7-3. I2C Pull-Ups and Pull-Downs
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
7.2 Utilized Features
8.1 Operating Conditions
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
8.3 Power Consumption Specifications
8.2 Electrical Specifications
Power and Clocking
Table 8-2. Absolute Maximum Ratings
Table 8-3. Power Consumption Specifications Sheet 1 of
Power and Clocking
8.4.1 32.768 kHz Oscillator Specifications
8.4 Oscillator Electrical Specifications
Power and Clocking
Table 8-3. Power Consumption Specifications Sheet 2 of
Power and Clocking
8.4.2 3.6864 MHz Oscillator Specifications
Table 8-4. 32.768 kHz Oscillator Specifications Sheet 2 of
Table 8-5. 3.6864 MHz Oscillator Specifications
8.5.1 Power Supply Connectivity
8.5 Reset and Power AC Timing Specifications
Power and Clocking
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 1 of
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 2 of
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 3 of
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 4 of
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 5 of
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
8.5.2 Power On Timing
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 6 of
8-11
Power and Clocking
8.5.3 Hardware Reset Timing
Figure 8-1. Power-On Reset Timing
JTAG PINS
8.5.5 GPIO Reset Timing
8.5.4 Watchdog Reset Timing
Power and Clocking
Figure 8-2. Hardware Reset Timing
Power and Clocking
8.5.6 Sleep Mode Timing
Table 8-9. GPIO Reset Timing Specifications
GPx PWREN VCC nVDDFAULT nRESETOUT
Power and Clocking
8.6 Memory Bus and PCMCIA AC Specifications
Table 8-10. Sleep Mode Timing Specifications Sheet 2 of
8-15
Table 8-12. Variable Latency I/O Interface AC Specifications
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Table 8-14. Synchronous Memory Interface AC Specifications 3.3
Power and Clocking
8-17
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
Table 8-16. Variable Latency I/O Interface AC Specifications 2.5
Power and Clocking
8-19
PXA250 and PXA210 Applications Processors Design Guide
8.7.1 Power System
8.7 Example Form Factor Reference Design Power Delivery Example
Power and Clocking
Table 8-18. Synchronous Memory Interface AC Specifications 2.5
Power and Clocking
8.7.1.1 Power System Configuration
8-21
8.7.3 PLL Power
8.7.2 CORE Power
Power and Clocking
Figure 8-5. Example Form Factor Reference Design Power System Design
8.7.5 Peripheral 5.5 V Power
8.7.4 I/O 3.3 V Power
Power and Clocking
8-23
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
JTAG/Debug Port
9.2 Schematics
9.1 Description
Figure 9-1. JTAG/Debug Port Wiring Diagram
JTAG/Debug Port
9.3 Layout
PXA250 and PXA210 Applications Processors Design Guide
Migration
SA-1110/Applications Processor
PXA250 and PXA210 Applications Processors Design Guide
A.1.2 Signal Changes
A.1 SA-1110 Hardware Migration Issues
A.1.1 Hardware Compatibility
Table A-1. PXA250 Boot Select Options Sheet 1 of
Figure A-1. Write Enable Control Pins
Table A-1. PXA250 Boot Select Options Sheet 2 of
SA-1110
PXA250
A.1.4 Package
A.1.3 Power Delivery
A.1.5 Clocks
SA-1110/Applications Processor Migration
A.1.6 UCB1300
A.2 SA-1110 to PXA250 Software Migration Issues
SA-1110/Applications Processor Migration
PXA250 and PXA210 Applications Processors Design Guide
A.2.1 Software Compatibility
A.2.4 Configuration registers
A.2.2 Address space
A.2.3 Page Table Changes
A.2.5 DMA
A.3 Using New PXA250 Features
SA-1110/Applications Processor Migration
PXA250 and PXA210 Applications Processors Design Guide
A.3.1 Intel XScale Microarchitecture
A.3.4 Other features
A.3.2 Debugging
A.3.3 Cache Attributes
SA-1110/Applications Processor Migration
A.3.5 Conclusion
PXA250 and PXA210 Applications Processors Design Guide
A-10
SA-1110/Applications Processor Migration
PXA250 and PXA210 Applications Processors Design Guide
B.2 Schematic Diagrams
Schematic Diagrams
Example Form Factor Reference Design
B.1 Notes
Page
Intel PXA250 Processor
Pg.2
Address and Data Buses
Pg.3
RESET
Intel PXA250 Processor
Capacitors for Core
SDRAM
SYSTEM CONFIGURATION REGISTER
SDRAM Bank Addressing
Resistor StrataFlash
Flash Memory
Synchronous
StrataFlash
Board Control
Buffer
Register
CPLD
74LVCH16245A
Transceivers
74LVCH16245A
74LVCH16245A
Audio Amp
Audio CODEC
UCB1400
Modem / Audio
Headset Jack
IrDA Transceiver
Microphone
Speaker
Three Position Switch
Momentary Switches
Base Station Connector
Compact Flash Type II Socket
JTAG ICE Connector
Connector
SD Socket
Radio
Battery Charger
Battery Connector
5.5 Volt Supply
Processor Core Voltage Supply
Note On
LCD CPLD
board Back
Light Inverter
Sharp LCD Connector
LCD Power
Connector
Toshiba LCD Connector
Expansion
Expansion
Header
Header
Revision Tracking Changes
B-18
Example Form Factor Reference Design Schematic Diagrams
PXA250 and PXA210 Applications Processors Design Guide
C.1 Schematic Diagram
Schematic Diagram
BBPXA2xx Development Baseboard
PXA250 and PXA210 Applications Processors Design Guide
BBPXA2xx
Table of Contents
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C-40
BBPXA2xx Development Baseboard Schematic Diagram
PXA250 and PXA210 Applications Processors Design Guide
Diagram
PXA250 Processor Card Schematic
D.1 Schematic Diagram
PXA250 and PXA210 Applications Processors Design Guide
DCPXA250 Processor Card 32-bit version
TABLE OF CONTENTS
7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER
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E.1 Schematic Diagram
PXA210 Processor Card Schematic
Diagram
The DCPXA210 processor card schematic is on the following pages
TABLE OF CONTENTS
DCPXA210 Processor Card 16-bit version
CONNECTOR MEMORY and I/O SIGNALS
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PXA250 and PXA210 Applications Processors Design Guide
PXA210 Processor Card Schematic Diagram
