Power and Clocking

Table 8-16. Variable Latency I/O Interface AC Specifications (2.5 V)

 

 

 

MEMCLK Frequency (MHz)

 

 

Symbol

Description

 

 

 

 

 

 

Notes

 

 

99.5

118.0

132.7

 

147.5

165.9

 

 

 

 

 

 

 

 

 

 

 

Variable Latency IO Interface (VLIO) (Asynchronous)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioAS

MA(25:0) setup to nCS asserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioASRW

MA(25:0) setup to nOE or nPWE asserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioAH

MA(25:0) hold after nOE or nPWE deasserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioCES

nCS setup to nOE or nPWE asserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioCEH

nCS hold after nOE or nPWE deasserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioDSW

MD(31:0), DQM(3:0) write data setup to nPWE asserted

 

 

 

 

 

 

 

 

 

 

 

TBD

 

 

 

tvlioDSWH

MD(31:0), DQM(3:0) write data setup to nPWE

 

 

 

 

 

 

 

 

 

 

 

 

deasserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioDHW

MD(31:0), DQM(3:0) hold after nPWE deasserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioDHR

MD(31:0) read data hold after nOE deasserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioRDYH

RDY hold after nOE, nPWE deasserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioNPWE

nPWE, nOE high time between beats of write or read

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTES:

1.This number represents 1 MEMCLK period

2.This number represents 2 MEMCLK periods

Table 8-17. Card Interface (PCMCIA or Compact Flash) AC Specifications (2.5 V)

Symbol

Description

MEMCLK Frequency (MHz)

99.5

118.0

132.7

147.5

165.9

 

 

 

 

 

Notes

Card Interface (PCMCIA or Compact Flash) (Asynchronous)

tcardAS

MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE,

 

nPOE, nPIOW, or nPIOR asserted

 

 

 

 

 

 

tcardAH

MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE,

 

nPOE, nPIOW, or nPIOR deasserted

 

 

 

 

 

 

tcardDS

MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR

TBD

asserted

 

 

 

 

 

 

tcardDH

MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR

 

deasserted

 

 

 

 

 

 

tcardCMD

nPWE, nPOE, nPIOW, or nPIOR command assertion

 

 

 

 

NOTE:

1. These numbers are minimums. They can be much longer based on the programmable Card Interface timing registers.

PXA250 and PXA210 Applications Processors Design Guide

8-19

Page 87
Image 87
Intel PXA250 and PXA210 manual Variable Latency I/O Interface AC Specifications 2.5

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.