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Intel PXA250 and PXA210 manual USB Interface, 1. Self Powered Device

Models: PXA250 and PXA210

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USB Interface

USB Interface

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4.1Self Powered Device

Figure 4-1shows the USB interface connection for a self-powered device. The 0 ohm resistors are optional, and if not used, then connect USB UDC+ directly to the device UDC+ and connect USB UDC- directly to device UDC-. The device UDC+ and UDC- pins match the impedance of a USB cable, 90 ohms, without the use of external series resistors. You may install 0 ohm resistors on your board to compensate for minor differences between the USB cable and your board trace impedance.

The 5 to 3.3 voltage divider is required since the device GPIO pins cannot exceed 3.3 V. This voltage divider can be implemented in a number of ways. The most robust and expensive solution is to use a MAX6348 Power-On-Reset device. This solution produces a very clean signal edge and minimizes signal bounce. The more inexpensive solution is to use a 3.3 V line buffer with 5 V tolerant inputs. This solution does not reduce signal bounce, so software must compensate by reading the GPIO signal after it stabilizes. A third solution is to implement a signal bounce minimization circuit that is 5 V tolerant, but produces a 3.3 V signal to the GPIO pin.

Note: If GPIOn and GPIOx are the same pin, never put the device to sleep while the USB cable is connected to the device. During sleep, the USB controller is in reset and will not respond to the host; after sleep, the device will not respond to its host-assigned address.

Figure 4-1. Self Powered Device

USB 5V

USB UDC+

USB UDC-

USB GND

5V to 3.3V

470K

GPIOn

GPIOx

1.5K

UDC+

0ohm

(optional)

UDC-

0ohm

(optional)

Board GND

4.1.1Operation if GPIOn and GPIOx are Different Pins

Any GPIO pins can be defined as GPIOn and GPIOx. GPIOn should be a GPIO which can bring the device out of sleep. Out of reset, configure GPIOx as an input that causes the UDC+ line to float. GPIOn is configured as an input that causes an interrupt whenever a rising or falling edge is

PXA250 and PXA210 Applications Processors Design Guide

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Intel PXA250 and PXA210 manual USB Interface, Self Powered Device, Operation if GPIOn and GPIOx are Different Pins

Contents

Order Number Design GuideIntel PXA250 and PXA210 Applications Processors FebruaryPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide ContentsContents USB InterfacePXA250 and PXA210 Applications Processors Design Guide ContentsMultiMediaCard MMC AC97Example Form Factor Reference Design Schematic Diagrams ContentsPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide FiguresTables ContentsPXA250 and PXA210 Applications Processors Design Guide ContentsPXA250 and PXA210 Applications Processors Design Guide ContentsTable 1-2. Related Documentation Introduction1.1 Functional Overview Revision HistoryOS Timer 1.2 Package Information1.2.1 Package Introduction Figure 1-1. Applications Processor Block DiagramPXA250 and PXA210 Applications Processors Design Guide IntroductionPXA250 and PXA210 Applications Processors Design Guide 1.2.2 Signal Pin DescriptionsTable 1-3. Signal Pin Descriptions Sheet 1 of IntroductionIntroduction Table 1-3. Signal Pin Descriptions Sheet 2 ofPXA250 and PXA210 Applications Processors Design Guide Introduction Table 1-3. Signal Pin Descriptions Sheet 3 ofPXA250 and PXA210 Applications Processors Design Guide Introduction Table 1-3. Signal Pin Descriptions Sheet 4 ofPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 5 ofBOOTSEL20 Description IntroductionIntroduction Table 1-3. Signal Pin Descriptions Sheet 6 ofPXA250 and PXA210 Applications Processors Design Guide Introduction Table 1-3. Signal Pin Descriptions Sheet 7 ofPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide IntroductionFigure 1-2. PXA250 Applications Processor 1-11PXA250 and PXA210 Applications Processors Design Guide Introduction1-13 IntroductionPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide IntroductionPXA250 and PXA210 Applications Processors Design Guide IntroductionFigure 1-3. PXA210 Applications Processor 1-15PXA250 and PXA210 Applications Processors Design Guide Introduction1-17 IntroductionPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide Introduction2.1 Overview System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide Card Memory Interface Figure 2-1. General Memory Interface ConfigurationSystem Memory Interface PXA250 and PXA210 Applications Processors Design GuideTable 2-1. Memory Address Map 2.3 SDRAM memory wiring diagram2.2 SDRAM Interface System Memory InterfaceFigure 2-2. SDRAM Memory System Example System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide 2.4 SDRAM SupportSystem Memory Interface Table 2-2. SDRAM Memory Types Supported by the Applications ProcessorPXA250 and PXA210 Applications Processors Design Guide 2.5 SDRAM Address MappingSystem Memory Interface Table 2-3. Normal Mode Memory Address MappingPXA250 and PXA210 Applications Processors Design Guide 2.6 Static Memory2.6.1 Overview System Memory InterfaceSystem Memory Interface 2.6.2 Boot Time DefaultsTable 2-5. Valid Booting Configurations Based on Package Type Table 2-6. BOOTSEL Definitions Sheet 1 ofSystem Memory Interface 2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options2.6.4 Variable Latency I/O Interface Overview Table 2-6. BOOTSEL Definitions Sheet 2 ofnCS0 System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide memlkSystem Memory Interface 2.6.5 External Logic for PCMCIA Implementation2-11 Socket System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide PXA250 Applications ProcessorSocket System Memory Interface2-13 PXA250Alternate Bus Master Mode Variable Latency I/O Flow through DMA 2.6.6 DMA / Companion Chip InterfaceSystem Memory Interface Connect a companion chip to the applications processor viaPXA250 PXA250Memory ControllerEXTERNAL SYSTEM PXA250System Memory Interface Figure 2-7. Variable Latency I/OCS, CKE, DQM CLK, MA 2.7 System Memory Layout Guidelines2.7.1 System Memory Topologies Min and Max Simulated Loading CS, CKE, DQM CLK, MAFigure 2-11. MD maximum loading topology 2.7.2 System Memory Recommended Trace LengthsTable 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals System Memory InterfaceTable 3-1. LCD Controller Data Pin Utilization Sheet 1 of LCD Display Controller3.1 LCD Display Overview 3.2 Passive DSTN DisplaysLCD Display Controller 3.2.1 Typical Connections for Passive Panel DisplaysTable 3-2. Passive Display Pins Required 3.2.1.1 Passive Monochrome Single Panel DisplaysPXA250 and PXA210 Applications Processor Design Guide 3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data3.2.1.3 Passive Monochrome Dual Panel Displays LCD Display ControllerFigure 3-3. Passive Monochrome Dual Panel Displays Typical Connection 3.2.1.4 Passive Color Single Panel Displays3.2.1.5 Passive Color Dual Panel Displays LCD Display ControllerPXA250 and PXA210 Applications Processor Design Guide 3.3 Active TFT DisplaysLCD Display Controller Figure 3-5. Passive Color Dual Panel Displays Typical ConnectionPXA250 and PXA210 Applications Processor Design Guide 3.3.1 Typical connections for Active Panel DisplaysTable 3-3. Active Display Pins Required LCD Display ControllerTable 3-4. PXA250 LCD Controller Ball Positions Sheet 1 of 3.4 PXA250 PinoutLCD Display Controller Figure 3-6. Active Color Display Typical Connection3.5.2 Backlight Inverter 3.5.3 Signal Routing and Buffering3.5 Additional Design Considerations 3.5.1 Contrast VoltageLCD Display Controller 3.5.4 Panel ConnectorPXA250 and PXA210 Applications Processor Design Guide PXA250 and PXA210 Applications Processor Design Guide LCD Display ControllerFigure 4-1. Self Powered Device 4.1 Self Powered Device4.1.1 Operation if GPIOn and GPIOx are Different Pins USB InterfacePXA250 and PXA210 Applications Processors Design Guide 4.2 Bus Powered Device4.1.2 Operation if GPIOn and GPIOx are the Same Pin USB InterfaceTable 5-1. MMC Signal Description 5.1 Schematics5.1.1 Signal Description MultiMediaCard MMCTable 5-3. MMC Controller Supported Sockets and Devices 5.1.2 How to WireTable 5-2. SDCard Socket Signals MultiMediaCard MMCMultiMediaCard MMC Figure 5-1. Applications Processor MMC and SDCard Signal ConnectionsPXA250 and PXA210 Applications Processors Design Guide 5.1.2.1 SDCard Socket5.1.2.2 MMC Socket MultiMediaCard MMCMultiMediaCard MMC 5.1.3 Simplified SchematicTable 5-4. SDCard Pull-up and Pull-down Resistors 5.2 Utilized Features5.1.4 Pull-up and Pull-down MultiMediaCard MMCPXA250 and PXA210 Applications Processors Design Guide 6.1 SchematicsAC97 Figure 6-1. AC97 connectionAC97 6.2 LayoutPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide 7.1 Schematics7.1.1 Signal Description Table 7-1. I2C Signal DescriptionPXA250 and PXA210 Applications Processors Design Guide 7.1.2 Digital-to-Analog Converter DAC7.1.3 Other Uses of I2C Figure 7-1. Linear Technology DAC with I2C InterfacePXA250 and PXA210 Applications Processors Design Guide 7.1.4 Pull-Ups and Pull-DownsFigure 7-2. Using an Analog Switch to Allow a Second CF Card Figure 7-3. I2C Pull-Ups and Pull-DownsPXA250 and PXA210 Applications Processors Design Guide 7.2 Utilized Features8.1 Operating Conditions Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Table 8-2. Absolute Maximum Ratings 8.2 Electrical Specifications8.3 Power Consumption Specifications Power and ClockingTable 8-3. Power Consumption Specifications Sheet 1 of Power and ClockingTable 8-3. Power Consumption Specifications Sheet 2 of 8.4 Oscillator Electrical Specifications8.4.1 32.768 kHz Oscillator Specifications Power and ClockingTable 8-5. 3.6864 MHz Oscillator Specifications 8.4.2 3.6864 MHz Oscillator SpecificationsPower and Clocking Table 8-4. 32.768 kHz Oscillator Specifications Sheet 2 ofTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 1 of 8.5 Reset and Power AC Timing Specifications8.5.1 Power Supply Connectivity Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 2 of Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 3 of Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 4 of Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 5 of Power and ClockingPXA250 and PXA210 Applications Processors Design Guide 8-11 8.5.2 Power On TimingPower and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 6 ofJTAG PINS 8.5.3 Hardware Reset TimingPower and Clocking Figure 8-1. Power-On Reset TimingFigure 8-2. Hardware Reset Timing 8.5.4 Watchdog Reset Timing8.5.5 GPIO Reset Timing Power and ClockingGPx PWREN VCC nVDDFAULT nRESETOUT 8.5.6 Sleep Mode TimingPower and Clocking Table 8-9. GPIO Reset Timing Specifications8-15 8.6 Memory Bus and PCMCIA AC SpecificationsPower and Clocking Table 8-10. Sleep Mode Timing Specifications Sheet 2 ofTable 8-12. Variable Latency I/O Interface AC Specifications Power and ClockingPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-14. Synchronous Memory Interface AC Specifications 3.3 8-17PXA250 and PXA210 Applications Processors Design Guide Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-16. Variable Latency I/O Interface AC Specifications 2.5 8-19Table 8-18. Synchronous Memory Interface AC Specifications 2.5 8.7 Example Form Factor Reference Design Power Delivery Example8.7.1 Power System Power and ClockingPower and Clocking 8.7.1.1 Power System Configuration8-21 Figure 8-5. Example Form Factor Reference Design Power System Design 8.7.2 CORE Power8.7.3 PLL Power Power and Clocking8-23 8.7.4 I/O 3.3 V Power8.7.5 Peripheral 5.5 V Power Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Power and ClockingFigure 9-1. JTAG/Debug Port Wiring Diagram 9.2 SchematicsJTAG/Debug Port 9.1 DescriptionJTAG/Debug Port 9.3 LayoutPXA250 and PXA210 Applications Processors Design Guide Migration SA-1110/Applications ProcessorPXA250 and PXA210 Applications Processors Design Guide Table A-1. PXA250 Boot Select Options Sheet 1 of A.1 SA-1110 Hardware Migration IssuesA.1.2 Signal Changes A.1.1 Hardware CompatibilityPXA250 Table A-1. PXA250 Boot Select Options Sheet 2 ofFigure A-1. Write Enable Control Pins SA-1110SA-1110/Applications Processor Migration A.1.3 Power DeliveryA.1.4 Package A.1.5 ClocksPXA250 and PXA210 Applications Processors Design Guide A.2 SA-1110 to PXA250 Software Migration IssuesA.1.6 UCB1300 SA-1110/Applications Processor MigrationA.2.3 Page Table Changes A.2.4 Configuration registersA.2.1 Software Compatibility A.2.2 Address spacePXA250 and PXA210 Applications Processors Design Guide A.3 Using New PXA250 FeaturesA.2.5 DMA SA-1110/Applications Processor MigrationA.3.3 Cache Attributes A.3.4 Other featuresA.3.1 Intel XScale Microarchitecture A.3.2 DebuggingSA-1110/Applications Processor Migration A.3.5 ConclusionPXA250 and PXA210 Applications Processors Design Guide A-10 SA-1110/Applications Processor MigrationPXA250 and PXA210 Applications Processors Design Guide B.1 Notes Schematic DiagramsB.2 Schematic Diagrams Example Form Factor Reference DesignPage Intel PXA250 Processor Pg.2Address and Data Buses Capacitors for Core RESETPg.3 Intel PXA250 ProcessorSDRAM SYSTEM CONFIGURATION REGISTERSDRAM Bank Addressing StrataFlash Flash MemoryResistor StrataFlash SynchronousCPLD BufferBoard Control Register74LVCH16245A Transceivers74LVCH16245A 74LVCH16245AModem / Audio Audio CODECAudio Amp UCB1400Speaker IrDA TransceiverHeadset Jack MicrophoneCompact Flash Type II Socket Momentary SwitchesThree Position Switch Base Station ConnectorRadio ConnectorJTAG ICE Connector SD SocketProcessor Core Voltage Supply Battery ConnectorBattery Charger 5.5 Volt SupplyLight Inverter LCD CPLDNote On board BackToshiba LCD Connector LCD PowerSharp LCD Connector ConnectorHeader ExpansionExpansion HeaderRevision Tracking Changes B-18 Example Form Factor Reference Design Schematic DiagramsPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide Schematic DiagramC.1 Schematic Diagram BBPXA2xx Development BaseboardBBPXA2xx Table of ContentsPage Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page C-40 BBPXA2xx Development Baseboard Schematic DiagramPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide PXA250 Processor Card SchematicDiagram D.1 Schematic DiagramDCPXA250 Processor Card 32-bit version TABLE OF CONTENTS7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER Page Page Page Page Page Page Page Page Page Page The DCPXA210 processor card schematic is on the following pages PXA210 Processor Card SchematicE.1 Schematic Diagram DiagramPAGE DCPXA210 Processor Card 16-bit versionTABLE OF CONTENTS CONNECTOR MEMORY and I/O SIGNALSPage Page Page Page Page Page Page Page Page Page Page Page PXA250 and PXA210 Applications Processors Design Guide PXA210 Processor Card Schematic Diagram