System Memory Interface

Table 2-1. Memory Address Map

0x6000 0000

Reserved Address Space

 

 

0x5C00 0000

Reserved Address Space

 

 

0x5800 0000

Reserved Address Space

 

 

0x5400 0000

Reserved Address Space

 

 

0x5000 0000

Reserved Address Space

 

 

0x4C00 0000

Reserved Address Space

 

 

0x4800 0000

Memory Mapped Registers (Memory Ctl)

 

 

0x4400 0000

Memory Mapped Registers (LCD)

 

 

0x4000 0000

Memory Mapped Registers (Peripherals)

 

 

0x3000 0000

PCMCIA/CF – Slot 1

 

 

0x2000 0000

PCMCIA/CF – Slot 0

 

 

0x1C00 0000

Reserved Address Space

 

 

0x1800 0000

Reserved Address Space

 

 

0x1400 0000

Static Chip Select 5

 

 

0x1000 0000

Static Chip Select 4

 

 

0x0C00 0000

Static Chip Select 3

 

 

0x0800 0000

Static Chip Select 2

 

 

0x0400 0000

Static Chip Select 1

 

 

0x0000 0000

Static Chip Select 0

 

 

2.2SDRAM Interface

The applications processor supports an SDRAM interface at a maximum frequency of 100 MHz. The SDRAM Interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is allocated 64 MBytes of the internal memory map. However, the actual size of each partition is dependent on the particular SDRAM configuration used. The four partitions are divided into two partition pairs: the 0/1 pair and the 2/3 pair. Both partitions within a pair (for example, partition 0 and partition 1) must be identical in size and configuration; however, the two pairs can be different. For example, the 0/1 pair can be 100 MHz SDRAM on a 32-bit data bus, while the 2/3 pair can be 50 MHz SDRAM on a 16-bit data bus.

Note: For proper SDRAM operation above 50 MHz, 22 ohm series resistors must be placed on the memory address lines.

2.3SDRAM memory wiring diagram

Figure 2-2, “SDRAM Memory System Example” on page 2-4is a wiring diagram example that shows a system using 1Mword x 16-bit x 4-bank SDRAM devices for a total of 48 Mbytes. Refer to Section 2.5, “SDRAM Address Mapping” on page 2-6to determine the individual SDRAM component address.

PXA250 and PXA210 Applications Processors Design Guide

2-3

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Intel PXA250 and PXA210 manual Sdram Interface, Sdram memory wiring diagram, Memory Address Map
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PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.
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