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PXA250 and PXA210 manual
Models:
PXA250 and PXA210
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Specs
1. Applications Processor Block Diagram
1. General Memory Interface Configuration
How to Wire
A.1 SA-1110 Hardware Migration Issues
1. Power-On Reset Timing
Boot Time Defaults
Signal Pin Descriptions
Battery Connector
Self Powered Device
Page 151
Image 151
Page 150
Page 152
Page 151
Image 151
Page 150
Page 152
Contents
Order Number
Design Guide
Intel PXA250 and PXA210 Applications Processors
February
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Contents
Contents
USB Interface
PXA250 and PXA210 Applications Processors Design Guide
Contents
MultiMediaCard MMC
AC97
Example Form Factor Reference Design Schematic Diagrams
Contents
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Figures
Tables
Contents
PXA250 and PXA210 Applications Processors Design Guide
Contents
PXA250 and PXA210 Applications Processors Design Guide
Contents
Table 1-2. Related Documentation
Introduction
1.1 Functional Overview
Revision History
OS Timer
1.2 Package Information
1.2.1 Package Introduction
Figure 1-1. Applications Processor Block Diagram
PXA250 and PXA210 Applications Processors Design Guide
Introduction
PXA250 and PXA210 Applications Processors Design Guide
1.2.2 Signal Pin Descriptions
Table 1-3. Signal Pin Descriptions Sheet 1 of
Introduction
Introduction
Table 1-3. Signal Pin Descriptions Sheet 2 of
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-3. Signal Pin Descriptions Sheet 3 of
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-3. Signal Pin Descriptions Sheet 4 of
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Table 1-3. Signal Pin Descriptions Sheet 5 of
BOOTSEL20 Description
Introduction
Introduction
Table 1-3. Signal Pin Descriptions Sheet 6 of
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-3. Signal Pin Descriptions Sheet 7 of
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Figure 1-2. PXA250 Applications Processor
1-11
PXA250 and PXA210 Applications Processors Design Guide
Introduction
1-13
Introduction
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Introduction
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Figure 1-3. PXA210 Applications Processor
1-15
PXA250 and PXA210 Applications Processors Design Guide
Introduction
1-17
Introduction
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Introduction
2.1 Overview
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
Card Memory Interface
Figure 2-1. General Memory Interface Configuration
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
Table 2-1. Memory Address Map
2.3 SDRAM memory wiring diagram
2.2 SDRAM Interface
System Memory Interface
Figure 2-2. SDRAM Memory System Example
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
2.4 SDRAM Support
System Memory Interface
Table 2-2. SDRAM Memory Types Supported by the Applications Processor
PXA250 and PXA210 Applications Processors Design Guide
2.5 SDRAM Address Mapping
System Memory Interface
Table 2-3. Normal Mode Memory Address Mapping
PXA250 and PXA210 Applications Processors Design Guide
2.6 Static Memory
2.6.1 Overview
System Memory Interface
System Memory Interface
2.6.2 Boot Time Defaults
Table 2-5. Valid Booting Configurations Based on Package Type
Table 2-6. BOOTSEL Definitions Sheet 1 of
System Memory Interface
2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options
2.6.4 Variable Latency I/O Interface Overview
Table 2-6. BOOTSEL Definitions Sheet 2 of
nCS0
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
memlk
System Memory Interface
2.6.5 External Logic for PCMCIA Implementation
2-11
Socket
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
PXA250 Applications Processor
Socket
System Memory Interface
2-13
PXA250
Alternate Bus Master Mode Variable Latency I/O Flow through DMA
2.6.6 DMA / Companion Chip Interface
System Memory Interface
Connect a companion chip to the applications processor via
PXA250
PXA250
Memory
Controller
EXTERNAL SYSTEM
PXA250
System Memory Interface
Figure 2-7. Variable Latency I/O
CS, CKE, DQM CLK, MA
2.7 System Memory Layout Guidelines
2.7.1 System Memory Topologies Min and Max Simulated Loading
CS, CKE, DQM CLK, MA
Figure 2-11. MD maximum loading topology
2.7.2 System Memory Recommended Trace Lengths
Table 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals
System Memory Interface
Table 3-1. LCD Controller Data Pin Utilization Sheet 1 of
LCD Display Controller
3.1 LCD Display Overview
3.2 Passive DSTN Displays
LCD Display Controller
3.2.1 Typical Connections for Passive Panel Displays
Table 3-2. Passive Display Pins Required
3.2.1.1 Passive Monochrome Single Panel Displays
PXA250 and PXA210 Applications Processor Design Guide
3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data
3.2.1.3 Passive Monochrome Dual Panel Displays
LCD Display Controller
Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection
3.2.1.4 Passive Color Single Panel Displays
3.2.1.5 Passive Color Dual Panel Displays
LCD Display Controller
PXA250 and PXA210 Applications Processor Design Guide
3.3 Active TFT Displays
LCD Display Controller
Figure 3-5. Passive Color Dual Panel Displays Typical Connection
PXA250 and PXA210 Applications Processor Design Guide
3.3.1 Typical connections for Active Panel Displays
Table 3-3. Active Display Pins Required
LCD Display Controller
Table 3-4. PXA250 LCD Controller Ball Positions Sheet 1 of
3.4 PXA250 Pinout
LCD Display Controller
Figure 3-6. Active Color Display Typical Connection
3.5.2 Backlight Inverter
3.5.3 Signal Routing and Buffering
3.5 Additional Design Considerations
3.5.1 Contrast Voltage
LCD Display Controller
3.5.4 Panel Connector
PXA250 and PXA210 Applications Processor Design Guide
PXA250 and PXA210 Applications Processor Design Guide
LCD Display Controller
Figure 4-1. Self Powered Device
4.1 Self Powered Device
4.1.1 Operation if GPIOn and GPIOx are Different Pins
USB Interface
PXA250 and PXA210 Applications Processors Design Guide
4.2 Bus Powered Device
4.1.2 Operation if GPIOn and GPIOx are the Same Pin
USB Interface
Table 5-1. MMC Signal Description
5.1 Schematics
5.1.1 Signal Description
MultiMediaCard MMC
Table 5-3. MMC Controller Supported Sockets and Devices
5.1.2 How to Wire
Table 5-2. SDCard Socket Signals
MultiMediaCard MMC
MultiMediaCard MMC
Figure 5-1. Applications Processor MMC and SDCard Signal Connections
PXA250 and PXA210 Applications Processors Design Guide
5.1.2.1 SDCard Socket
5.1.2.2 MMC Socket
MultiMediaCard MMC
MultiMediaCard MMC
5.1.3 Simplified Schematic
Table 5-4. SDCard Pull-up and Pull-down Resistors
5.2 Utilized Features
5.1.4 Pull-up and Pull-down
MultiMediaCard MMC
PXA250 and PXA210 Applications Processors Design Guide
6.1 Schematics
AC97
Figure 6-1. AC97 connection
AC97
6.2 Layout
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
7.1 Schematics
7.1.1 Signal Description
Table 7-1. I2C Signal Description
PXA250 and PXA210 Applications Processors Design Guide
7.1.2 Digital-to-Analog Converter DAC
7.1.3 Other Uses of I2C
Figure 7-1. Linear Technology DAC with I2C Interface
PXA250 and PXA210 Applications Processors Design Guide
7.1.4 Pull-Ups and Pull-Downs
Figure 7-2. Using an Analog Switch to Allow a Second CF Card
Figure 7-3. I2C Pull-Ups and Pull-Downs
PXA250 and PXA210 Applications Processors Design Guide
7.2 Utilized Features
8.1 Operating Conditions
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Table 8-2. Absolute Maximum Ratings
8.2 Electrical Specifications
8.3 Power Consumption Specifications
Power and Clocking
Table 8-3. Power Consumption Specifications Sheet 1 of
Power and Clocking
Table 8-3. Power Consumption Specifications Sheet 2 of
8.4 Oscillator Electrical Specifications
8.4.1 32.768 kHz Oscillator Specifications
Power and Clocking
Table 8-5. 3.6864 MHz Oscillator Specifications
8.4.2 3.6864 MHz Oscillator Specifications
Power and Clocking
Table 8-4. 32.768 kHz Oscillator Specifications Sheet 2 of
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 1 of
8.5 Reset and Power AC Timing Specifications
8.5.1 Power Supply Connectivity
Power and Clocking
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 2 of
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 3 of
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 4 of
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 5 of
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
8-11
8.5.2 Power On Timing
Power and Clocking
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 6 of
JTAG PINS
8.5.3 Hardware Reset Timing
Power and Clocking
Figure 8-1. Power-On Reset Timing
Figure 8-2. Hardware Reset Timing
8.5.4 Watchdog Reset Timing
8.5.5 GPIO Reset Timing
Power and Clocking
GPx PWREN VCC nVDDFAULT nRESETOUT
8.5.6 Sleep Mode Timing
Power and Clocking
Table 8-9. GPIO Reset Timing Specifications
8-15
8.6 Memory Bus and PCMCIA AC Specifications
Power and Clocking
Table 8-10. Sleep Mode Timing Specifications Sheet 2 of
Table 8-12. Variable Latency I/O Interface AC Specifications
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
Table 8-14. Synchronous Memory Interface AC Specifications 3.3
8-17
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
Table 8-16. Variable Latency I/O Interface AC Specifications 2.5
8-19
Table 8-18. Synchronous Memory Interface AC Specifications 2.5
8.7 Example Form Factor Reference Design Power Delivery Example
8.7.1 Power System
Power and Clocking
Power and Clocking
8.7.1.1 Power System Configuration
8-21
Figure 8-5. Example Form Factor Reference Design Power System Design
8.7.2 CORE Power
8.7.3 PLL Power
Power and Clocking
8-23
8.7.4 I/O 3.3 V Power
8.7.5 Peripheral 5.5 V Power
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
Figure 9-1. JTAG/Debug Port Wiring Diagram
9.2 Schematics
JTAG/Debug Port
9.1 Description
JTAG/Debug Port
9.3 Layout
PXA250 and PXA210 Applications Processors Design Guide
Migration
SA-1110/Applications Processor
PXA250 and PXA210 Applications Processors Design Guide
Table A-1. PXA250 Boot Select Options Sheet 1 of
A.1 SA-1110 Hardware Migration Issues
A.1.2 Signal Changes
A.1.1 Hardware Compatibility
PXA250
Table A-1. PXA250 Boot Select Options Sheet 2 of
Figure A-1. Write Enable Control Pins
SA-1110
SA-1110/Applications Processor Migration
A.1.3 Power Delivery
A.1.4 Package
A.1.5 Clocks
PXA250 and PXA210 Applications Processors Design Guide
A.2 SA-1110 to PXA250 Software Migration Issues
A.1.6 UCB1300
SA-1110/Applications Processor Migration
A.2.3 Page Table Changes
A.2.4 Configuration registers
A.2.1 Software Compatibility
A.2.2 Address space
PXA250 and PXA210 Applications Processors Design Guide
A.3 Using New PXA250 Features
A.2.5 DMA
SA-1110/Applications Processor Migration
A.3.3 Cache Attributes
A.3.4 Other features
A.3.1 Intel XScale Microarchitecture
A.3.2 Debugging
SA-1110/Applications Processor Migration
A.3.5 Conclusion
PXA250 and PXA210 Applications Processors Design Guide
A-10
SA-1110/Applications Processor Migration
PXA250 and PXA210 Applications Processors Design Guide
B.1 Notes
Schematic Diagrams
B.2 Schematic Diagrams
Example Form Factor Reference Design
Page
Intel PXA250 Processor
Pg.2
Address and Data Buses
Capacitors for Core
RESET
Pg.3
Intel PXA250 Processor
SDRAM
SYSTEM CONFIGURATION REGISTER
SDRAM Bank Addressing
StrataFlash
Flash Memory
Resistor StrataFlash
Synchronous
CPLD
Buffer
Board Control
Register
74LVCH16245A
Transceivers
74LVCH16245A
74LVCH16245A
Modem / Audio
Audio CODEC
Audio Amp
UCB1400
Speaker
IrDA Transceiver
Headset Jack
Microphone
Compact Flash Type II Socket
Momentary Switches
Three Position Switch
Base Station Connector
Radio
Connector
JTAG ICE Connector
SD Socket
Processor Core Voltage Supply
Battery Connector
Battery Charger
5.5 Volt Supply
Light Inverter
LCD CPLD
Note On
board Back
Toshiba LCD Connector
LCD Power
Sharp LCD Connector
Connector
Header
Expansion
Expansion
Header
Revision Tracking Changes
B-18
Example Form Factor Reference Design Schematic Diagrams
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Schematic Diagram
C.1 Schematic Diagram
BBPXA2xx Development Baseboard
BBPXA2xx
Table of Contents
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C-40
BBPXA2xx Development Baseboard Schematic Diagram
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
PXA250 Processor Card Schematic
Diagram
D.1 Schematic Diagram
DCPXA250 Processor Card 32-bit version
TABLE OF CONTENTS
7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER
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The DCPXA210 processor card schematic is on the following pages
PXA210 Processor Card Schematic
E.1 Schematic Diagram
Diagram
PAGE
DCPXA210 Processor Card 16-bit version
TABLE OF CONTENTS
CONNECTOR MEMORY and I/O SIGNALS
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PXA250 and PXA210 Applications Processors Design Guide
PXA210 Processor Card Schematic Diagram
