Introduction

Table 1-3. Signal Pin Descriptions (Sheet 2 of 7)

Name

Type

Description

 

 

 

nCS[5]/

ICOCZ

 

GPIO[33]

 

 

 

 

 

 

nCS[4]/

ICOCZ

Static chip selects. These signals are chip selects to static memory devices such as

GPIO[80]

 

ROM and Flash. They are individually programmable in the memory configuration

 

 

nCS[3]/

ICOCZ

registers. nCS[5:3] may be used with variable data latency variable latency I/O

GPIO[79]

devices.

 

See Note [2]

 

 

nCS[2]/

ICOCZ

 

GPIO[78]

 

 

 

 

 

 

nCS[1]/

ICOCZ

 

GPIO[15]

 

 

 

 

 

 

nCS[0]

ICOCZ

Static chip select 0. This is the chip select for the boot memory. nCS[0] is a dedicated

pin.

 

 

 

 

 

RD/nWR

OCZ

Read/Write for static interface. Intended for use as a steering signal for buffering logic

 

 

 

RDY/

ICOCZ

Variable Latency I/O Ready pin (input)

GPIO[18]

See Note [2]

 

 

 

 

MBGNT/GP[13]

ICOCZ

Memory Controller grant. (output) Notifies an external device that it has been granted

the system bus.

 

 

 

 

 

MBREQ/GP[14]

ICOCZ

Memory Controller alternate bus master request. (input) Allows an external device to

request the system bus from the Memory Controller.

 

 

 

 

 

PCMCIA/CF Control Pins - PXA250 Applications Processor only

 

 

 

 

 

PCMCIA output enable. Output PCMCIA signal that performs reads from memory and

nPOE/ GPIO[48]

ICOCZ

attribute space.

 

 

See Note [2]

 

 

 

nPWE/

 

PCMCIA write enable. Output signal that performs writes to memory and attribute

ICOCZ

space.

GPIO[49]

 

See Note [2]

 

 

 

 

 

nPIOW/

 

PCMCIA I/O write. Output signal that performs write transactions to the PCMCIA I/O

ICOCZ

space.

GPIO[51]

 

See Note [2]

 

 

 

 

 

nPIOR/

 

PCMCIA I/O read. Output signal that performs read transactions from the PCMCIA I/O

ICOCZ

space.

GPIO[50]

 

See Note [2]

 

 

 

 

 

nPCE[2:1]/

 

PCMCIA card enable. Output signals that selects a PCMCIA card. Bit one enables the

ICOCZ

high byte lane and bit zero enables the low byte lane.

GPIO[53, 52]

 

See Note [2]

 

 

 

 

 

nIOIS16/

 

I/O Select 16. Input signal from the PCMCIA card that indicates the current address is

ICOCZ

a valid 16 bit wide I/O address.

GPIO[57]

 

See Note [2]

 

 

 

 

 

nPWAIT/

 

PCMCIA wait. Input signal that is driven low by the PCMCIA card to extend the length

ICOCZ

of the transfers to/from the applications processor.

GPIO[56]

 

See Note [2]

 

 

 

 

 

 

 

PCMCIA socket select. Output signal used by external steering logic to route control,

nPSKTSEL/

 

address, and data signals to one of the two PCMCIA sockets. When PSKTSEL is low,

ICOCZ

socket zero is selected. When PSKTSEL is high, socket one is selected. This signal

GPIO[54]

 

has the same timing as address.

 

 

See Note [2]

 

 

 

PXA250 and PXA210 Applications Processors Design Guide

1-5

Page 12 Page 14
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Image 13
Intel PXA250 and PXA210 manual Signal Pin Descriptions Sheet 2, RDY Icocz, MBGNT/GP13 Icocz, MBREQ/GP14 Icocz
Page 12 Page 14

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.
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