8

7

6

5

4

3

2

1

D

C

Copyright 2002 Intel Corporation

{2,5,7} SA_A10 {2,5,7} SA_A11 {2,5,7} SA_A12 {2,5,7} SA_A13 {2,5,7} SA_A14 {2,5,7} SA_A15 {2,5,7} SA_A16 {2,5,7} SA_A17 {2,5,7} SA_A18 {2,5,7} SA_A19 {2,5,7} SA_A20 {2,5,7} SA_A21 {2,5,7} SA_A24

{2,7} SA_nSDCS_0

{2,5,6,7,10}SA_nWE

{2,5,6,7} SA_nSDCAS

{2,6,7} SA_nSDRAS

{2,7} SA_SDCLK_1

{2,6} SA_SDCKE_1

{2,5,7}SA_A23

{2,5,7}SA_A22

DC3P3V {2,7} SA_DQM_0

{2,7} SA_DQM_1

C17

0.1UF

C18

0.1UF

 

U4

 

 

 

 

23

A0

 

 

 

 

24

 

 

 

 

A1

4M x 4 x 16

 

25

 

A2

 

26

 

SDRAM

 

A3

 

 

29

 

 

 

 

A4

 

 

 

 

30

 

 

 

 

A5

 

 

 

 

31

 

 

 

 

A6

 

 

 

 

32

 

 

 

 

A7

 

 

 

 

33

 

 

 

 

A8

 

 

 

 

34

 

 

 

 

A9

 

 

 

 

22

 

 

 

 

A10

 

 

 

 

35

 

 

NC

40

A11

 

 

36

 

 

 

A12

 

 

 

2

 

 

 

D0

 

 

 

 

 

 

 

 

4

 

 

 

 

D1

19

 

 

 

5

nCS

 

 

D2

16

 

 

7

nWE

 

 

D3

17

 

 

8

nCAS

 

 

D4

18

 

 

10

nRAS

 

 

D5

 

 

 

11

 

 

 

 

D6

 

 

 

 

13

 

 

 

 

D7

38

 

 

 

42

CLK

 

 

D8

37

 

 

44

CKE

 

 

D9

20

 

 

45

BS_0

 

 

D10

21

 

 

47

BS_1

 

 

D11

15

 

 

48

LDQM

 

D12

39

 

50

UDMQ

 

D13

 

 

51

 

 

 

 

D14

 

 

 

 

53

1

 

 

 

D15

VDD_1

 

 

 

 

 

14

 

VSS_1

28

VDD_2

 

27

 

41

VDD_3

 

VSS_2

 

 

54

 

 

 

 

VSS_3

3

 

 

 

6

VDD_Q1

VSSQ_1

9

12

VDD_Q2

VSSQ_2

43

46

VDD_Q3

VSSQ_3

49

52

VDD_Q4

VSSQ_4

 

 

 

U5

 

 

 

 

SDRAM

SDRAM Bank Addressing:

SDRAM Address Bus wired for SA1110 legacy compatibility mode for SDRAM Bank Addressing.

SA_D0 {2,5,6,7}

SA_D1 {2,5,6,7}

SA_D2 {2,5,6,7}

SA_D3 {2,5,6,7}

SA_D4 {2,5,6,7}

SA_D5 {2,5,6,7}

SA_D6 {2,5,6,7}

SA_D7 {2,5,6,7}

SA_D8 {2,5,6,7}

SA_D9 {2,5,6,7}

SA_D10 {2,5,6,7}

SA_D11 {2,5,6,7}

SA_D12 {2,5,6,7}

SA_D13 {2,5,6,7}

SA_D14 {2,5,6,7}

SA_D15 {2,5,6,7}

Pg. 4

SYSTEM CONFIGURATION REGISTER

DC3P3V

R28

10K

DNI

 

 

R29

 

 

 

SD_SZ_0

{3,13} L_DD_8

 

 

 

 

100K

 

DC3P3V

 

R30

 

 

0

 

 

 

 

 

R31

10K

DNI

{3,13} L_DD_9

 

R32

 

SD_SZ_1

 

100K

 

 

DC3P3V

 

 

R33

 

 

 

 

0

 

R34

10K

DNI

 

 

R35

 

 

 

FLASH_SZ_0

{3,13} L_DD_10

 

 

 

 

100K

 

DC3P3V

 

R36

 

 

0

 

 

 

 

 

R37

10K

DNI

{3,13} L_DD_11

 

R38

 

FLASH_SZ_1

 

100K

 

 

 

 

 

 

DC3P3V

R39

0

 

 

 

 

D

C

 

{2,5,7}

 

SA_A10

 

 

23

A0

 

 

 

 

 

 

 

 

R40

10K

 

 

 

 

 

 

{2,5,7}

 

SA_A11

 

 

25

A1

4M x 4 x 16

 

 

 

 

 

 

DNI

 

 

 

 

 

 

 

 

 

 

 

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{2,5,7}

 

SA_A12

 

 

26

A2

SDRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{2,5,7}

 

SA_A13

 

 

A3

 

 

 

 

 

R41

 

 

 

 

FLASH_TYPE

 

 

 

 

 

 

29

 

 

 

 

 

{3,13}

 

 

 

 

 

 

 

 

{2,5,7}

 

SA_A14

 

 

30

A4

 

 

 

 

 

L_DD_12

 

 

 

 

 

 

 

 

{2,5,7}

 

SA_A15

 

 

A5

 

 

 

 

 

 

 

100K

 

DC3P3V

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

 

 

 

 

 

{2,5,7}

 

SA_A16

 

 

A6

 

 

 

 

 

 

 

 

R42

 

 

 

 

 

 

 

 

32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{2,5,7}

 

SA_A17

 

 

A7

 

 

 

 

 

 

 

 

0

 

 

 

 

 

B

 

 

 

33

 

 

 

 

 

 

 

 

 

 

 

 

B

{2,5,7}

 

SA_A18

 

 

A8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

34

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{2,5,7}

 

SA_A19

 

 

A9

 

 

 

 

 

 

 

 

 

 

R43

10K

 

 

 

 

 

 

 

35

 

 

40

 

 

 

 

 

 

 

DNI

 

 

 

{2,5,7}

 

SA_A20

 

 

22

A10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{2,5,7}

 

SA_A21

 

 

36

A11

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{2,5,7}

 

SA_A24

 

 

A12

 

 

2

 

 

 

 

 

 

 

R44

 

 

 

 

 

 

 

 

 

 

D0

SA_D16

{2,5,7}

{3,13}

L_DD_13

 

 

 

LCD_TYPE

{13}

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D1

SA_D17

{2,5,7}

 

 

 

DC3P3V

100K

 

 

 

 

 

 

 

 

 

 

 

19

 

 

5

 

 

 

 

 

 

 

 

{2,7}

SA_nSDCS_0

 

 

nCS

 

D2

SA_D18

{2,5,7}

 

 

 

R45

 

 

 

 

 

 

 

16

 

7

 

 

 

 

 

 

 

 

 

{2,5,6,7,10}

 

SA_nWE

 

 

nWE

 

D3

SA_D19

{2,5,7}

 

 

 

 

 

0

 

 

 

 

 

 

17

 

8

 

 

 

 

 

 

 

 

 

{2,5,6,7}

SA_nSDCAS

 

 

nCAS

 

D4

SA_D20

{2,5,7}

 

 

 

 

 

 

 

 

 

 

 

 

 

18

 

10

 

 

 

 

 

 

 

 

 

 

 

{2,6,7}

SA_nSDRAS

 

 

nRAS

 

D5

SA_D21

{2,5,7}

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D6

SA_D22

{2,5,7}

 

 

 

R46

10K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D7

SA_D23

{2,5,7}

 

 

 

 

 

 

 

 

 

{2,7}

SA_SDCLK_1

 

 

38

CLK

 

D8

42

SA_D24

{2,5,7}

 

 

 

 

 

 

 

 

 

 

 

 

 

37

 

44

 

 

 

 

 

 

 

 

 

 

 

{2,6}

SA_SDCKE_1

 

 

CKE

 

D9

SA_D25

{2,5,7}

 

 

 

R47

 

 

 

 

 

 

 

 

 

20

 

45

 

 

 

 

 

 

 

 

 

 

{2,5,7}

 

SA_A23

 

 

BS_0

 

D10

SA_D26

{2,5,7}

{3,13}

L_DD_14

 

 

 

 

nGFX_PRESENT {13,15}

 

 

 

 

21

 

47

 

 

 

 

 

{2,5,7}

 

SA_A22

 

 

BS_1

 

D11

SA_D27

{2,5,7}

 

 

 

100K

 

DC3P3V

 

 

 

 

 

 

 

15

 

48

 

 

 

 

 

 

 

DC3P3V

{2,7}

SA_DQM_2

 

 

LDQM

D12

SA_D28

{2,5,7}

 

 

 

 

 

 

 

 

 

 

39

50

 

 

 

 

 

 

 

 

 

 

 

{2,7}

SA_DQM_3

 

 

UDMQ

D13

SA_D29

{2,5,7}

 

 

 

 

 

 

 

 

 

 

 

 

 

 

51

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D14

SA_D30

{2,5,7}

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

53

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

D15

SA_D31

{2,5,7}

 

 

 

 

 

R49

10K

 

 

 

 

 

 

 

 

 

 

VDD_1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

VDD_2

VSS_1

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

41

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

VDD_3

VSS_2

 

 

 

 

 

 

 

R50

 

 

 

A

 

 

 

 

 

 

 

54

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS_3

 

 

 

{3,13}

L_DD_15

 

 

 

 

nNEP_PRESENT

{13,15}

 

 

 

 

0.1UF

 

0.1UF

3

 

 

6

 

 

 

 

 

 

 

 

 

 

C19

C20

VDD_Q1

VSSQ_1

 

 

 

 

 

 

 

100K

 

 

 

 

 

 

 

43

46

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

VDD_Q2

VSSQ_2

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

49

VDD_Q3

VSSQ_3

52

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD_Q4

VSSQ_4

 

 

 

 

 

 

PXA250 Processor Reference Design

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Size

Rev

B

2.07

 

 

 

 

 

Date:

Tuesday, February 05, 2002

Sheet

4

of

16

8

7

6

5

4

3

2

 

 

1

 

Page 109
Image 109
Intel PXA250 and PXA210 manual Sdram

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.