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Intel PXA250 and PXA210 manual SD Socket, Radio, Baseband, JTAG ICE Connector

Models: PXA250 and PXA210

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Page 116

SD Socket

8

7

6

5

4

3

2

1

Copyright 2002 Intel Corporation

Pg. 11

SD Socket

DC3P3V

D

J10

R147

10K

D

Bottom Mount

SA_MMCMD {2}

LAYOUT NOTE: Place close to

9

DAT2

Battery Header and Codec UCB

1

CD_DAT3

MMC_CS0 {2}

1400

C91

0.1UF

CMD

2

Radio

VSS1

3

C132

Baseband

VDD

4

MMC_PWR

{8} LINE_OUT_L

Connector

CLK

5

SA_MMCCLK

{2}

DNI IF MMC

0.1UF

J20

R225

C140

VSS2

6

{8} LINE_OUT_R

1

2

!!

0

C

CHECK

10

11

12

7

R226

0

IF

R227

100K

{2,15}

SA_BT_TXD

9

10

RADIO_RI

{2}

C

DAT0

SA_MMDAT

{2}

DC3P3V

0.1UF

3

4

RADIO_DSR

{2}

WP

COMM

CD

8

R150

IF

{2}

SA_BT_RTS

5

6

SA_BT_RXD

{2,15}

7

8

DAT1

DC3P3V

DNI

{2}

RADIO_DTR

SA_BT_CTS

{2}

SD

DNI

47.5K

SD

11

12

{6} RADIO_PWR_ON

RADIO_RXD_C

{2}

nMMC_DETECT {2,13}

13

14

nRESET_IN

{3,10,15}

DC3P3V

DC3P3V

{6} RADIO_WAKE

CARD Selection Resistors

RADIO_SPKRN

DNI

{2}

RADIO_DCD

15

16

and Values

DNI

0

R228

100K

17

18

R226

MMC

{8,9}

MICGND

RADIO_SPKRP

{8}

RES

SD

MMC

IF

MMC_WP

{2}

R227

DNI

100K

{9}

RADIO_MICP

19

20

R225

0

DNI

DC5P5V

{3,6,13,15}

nRESET_OUT

21

22

R228

100K

DNI

R229

100K

23

24

{3,8,10,12,13,14}

VBATT

AC97_GPIO_0 {8}

DC5P5V

U27

{3,8,10,12,13,14}

VBATT

25

26

AC97_GPIO_1

{8}

R198

27

28

AC97_GPIO_2

{8}

MIC5207-3.3BM5

0

3.3V LDO REG

29

30

1

5

MMC_PWR

{8}

AC97_GPIO_4

AC97_GPIO_3

{8}

180ma

VOUT

VIN

B

2

GND

4.7UF

1

+

B

{13}

MMC_ON

3

EN

BYP

4

C92

LE33

2

JTAG ICE Connector

DC3P3V

DC3P3V

J19

{2,10}

GPIO_22

DNI R236

R270

10K

R221

0

R219

1

2

{3,6,10,13}

JTAG_TMS

DVAL_1

{15}

0

0

{3} JTAG_nTRST

3

4

{2,10}

GPIO_21

R233

0

R218

{6,10}

CPLD1_TDI

5

6

{6,10}

CPLD1_TDI

DVAL_0

{15}

R234

0

DNI

R222

100K

{3,6,10,13}

JTAG_TMS

7

8

{2,10}

GPIO_19

0

R232

{3,6,10,13}

JTAG_TCK

9

10

{3,6,10,13}

JTAG_TCK

DREQ_1

{15}

R235

0

11

12

{2,10}

GPIO_20

0

R231

{3,10}

SA_TDO

R223

13

14

{3,10}

SA_TDO

DREQ_0

{15}

A

A

75

R224

0

{3,10,15}

nRESET_IN

15

16

0

17

18

19

20

PXA250 Processor Reference Design

					Size					Rev
					B					2.07
					Date:	Tuesday, February 05, 2002	Sheet	11	of	16
8	7	6	5	4	3	2			1

Image 116

Intel PXA250 and PXA210 manual SD Socket, Radio, Baseband, JTAG ICE Connector

Contents

Design Guide Intel PXA250 and PXA210 Applications ProcessorsFebruary Order NumberPXA250 and PXA210 Applications Processors Design Guide Contents ContentsUSB Interface PXA250 and PXA210 Applications Processors Design GuideContents MultiMediaCard MMCAC97 PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide ContentsExample Form Factor Reference Design Schematic Diagrams Figures TablesContents PXA250 and PXA210 Applications Processors Design GuideContents PXA250 and PXA210 Applications Processors Design GuideContents PXA250 and PXA210 Applications Processors Design GuideIntroduction 1.1 Functional OverviewRevision History Table 1-2. Related Documentation1.2 Package Information 1.2.1 Package IntroductionFigure 1-1. Applications Processor Block Diagram OS TimerIntroduction PXA250 and PXA210 Applications Processors Design Guide1.2.2 Signal Pin Descriptions Table 1-3. Signal Pin Descriptions Sheet 1 ofIntroduction PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 2 ofIntroduction PXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 3 ofIntroduction PXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 4 ofIntroduction Table 1-3. Signal Pin Descriptions Sheet 5 of BOOTSEL20 DescriptionIntroduction PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 6 ofIntroduction PXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 7 ofIntroduction Introduction Figure 1-2. PXA250 Applications Processor1-11 PXA250 and PXA210 Applications Processors Design GuideIntroduction PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Introduction1-13 Introduction PXA250 and PXA210 Applications Processors Design GuideIntroduction Figure 1-3. PXA210 Applications Processor1-15 PXA250 and PXA210 Applications Processors Design GuideIntroduction PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Introduction1-17 Introduction PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide System Memory Interface2.1 Overview Figure 2-1. General Memory Interface Configuration System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide Card Memory Interface2.3 SDRAM memory wiring diagram 2.2 SDRAM InterfaceSystem Memory Interface Table 2-1. Memory Address MapPXA250 and PXA210 Applications Processors Design Guide System Memory InterfaceFigure 2-2. SDRAM Memory System Example 2.4 SDRAM Support System Memory InterfaceTable 2-2. SDRAM Memory Types Supported by the Applications Processor PXA250 and PXA210 Applications Processors Design Guide2.5 SDRAM Address Mapping System Memory InterfaceTable 2-3. Normal Mode Memory Address Mapping PXA250 and PXA210 Applications Processors Design Guide2.6 Static Memory 2.6.1 OverviewSystem Memory Interface PXA250 and PXA210 Applications Processors Design Guide2.6.2 Boot Time Defaults Table 2-5. Valid Booting Configurations Based on Package TypeTable 2-6. BOOTSEL Definitions Sheet 1 of System Memory Interface2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options 2.6.4 Variable Latency I/O Interface OverviewTable 2-6. BOOTSEL Definitions Sheet 2 of System Memory InterfaceSystem Memory Interface PXA250 and PXA210 Applications Processors Design Guidememlk nCS02-11 2.6.5 External Logic for PCMCIA ImplementationSystem Memory Interface System Memory Interface PXA250 and PXA210 Applications Processors Design GuidePXA250 Applications Processor SocketSystem Memory Interface 2-13PXA250 Socket2.6.6 DMA / Companion Chip Interface System Memory InterfaceConnect a companion chip to the applications processor via Alternate Bus Master Mode Variable Latency I/O Flow through DMAPXA250 MemoryController PXA250PXA250 System Memory InterfaceFigure 2-7. Variable Latency I/O EXTERNAL SYSTEM2.7 System Memory Layout Guidelines 2.7.1 System Memory Topologies Min and Max Simulated LoadingCS, CKE, DQM CLK, MA CS, CKE, DQM CLK, MA2.7.2 System Memory Recommended Trace Lengths Table 2-10. Minimum and Maximum Trace Lengths for the SDRAM SignalsSystem Memory Interface Figure 2-11. MD maximum loading topologyLCD Display Controller 3.1 LCD Display Overview3.2 Passive DSTN Displays Table 3-1. LCD Controller Data Pin Utilization Sheet 1 of3.2.1 Typical Connections for Passive Panel Displays Table 3-2. Passive Display Pins Required3.2.1.1 Passive Monochrome Single Panel Displays LCD Display Controller3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data 3.2.1.3 Passive Monochrome Dual Panel DisplaysLCD Display Controller PXA250 and PXA210 Applications Processor Design Guide3.2.1.4 Passive Color Single Panel Displays 3.2.1.5 Passive Color Dual Panel DisplaysLCD Display Controller Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection3.3 Active TFT Displays LCD Display ControllerFigure 3-5. Passive Color Dual Panel Displays Typical Connection PXA250 and PXA210 Applications Processor Design Guide3.3.1 Typical connections for Active Panel Displays Table 3-3. Active Display Pins RequiredLCD Display Controller PXA250 and PXA210 Applications Processor Design Guide3.4 PXA250 Pinout LCD Display ControllerFigure 3-6. Active Color Display Typical Connection Table 3-4. PXA250 LCD Controller Ball Positions Sheet 1 of3.5.3 Signal Routing and Buffering 3.5 Additional Design Considerations3.5.1 Contrast Voltage 3.5.2 Backlight InverterPXA250 and PXA210 Applications Processor Design Guide 3.5.4 Panel ConnectorLCD Display Controller LCD Display Controller PXA250 and PXA210 Applications Processor Design Guide4.1 Self Powered Device 4.1.1 Operation if GPIOn and GPIOx are Different PinsUSB Interface Figure 4-1. Self Powered Device4.2 Bus Powered Device 4.1.2 Operation if GPIOn and GPIOx are the Same PinUSB Interface PXA250 and PXA210 Applications Processors Design Guide5.1 Schematics 5.1.1 Signal DescriptionMultiMediaCard MMC Table 5-1. MMC Signal Description5.1.2 How to Wire Table 5-2. SDCard Socket SignalsMultiMediaCard MMC Table 5-3. MMC Controller Supported Sockets and DevicesFigure 5-1. Applications Processor MMC and SDCard Signal Connections MultiMediaCard MMC5.1.2.1 SDCard Socket 5.1.2.2 MMC SocketMultiMediaCard MMC PXA250 and PXA210 Applications Processors Design Guide5.1.3 Simplified Schematic MultiMediaCard MMC5.2 Utilized Features 5.1.4 Pull-up and Pull-downMultiMediaCard MMC Table 5-4. SDCard Pull-up and Pull-down Resistors6.1 Schematics AC97Figure 6-1. AC97 connection PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide 6.2 LayoutAC97 7.1 Schematics 7.1.1 Signal DescriptionTable 7-1. I2C Signal Description PXA250 and PXA210 Applications Processors Design Guide7.1.2 Digital-to-Analog Converter DAC 7.1.3 Other Uses of I2CFigure 7-1. Linear Technology DAC with I2C Interface PXA250 and PXA210 Applications Processors Design Guide7.1.4 Pull-Ups and Pull-Downs Figure 7-2. Using an Analog Switch to Allow a Second CF CardFigure 7-3. I2C Pull-Ups and Pull-Downs PXA250 and PXA210 Applications Processors Design Guide7.2 Utilized Features PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Power and Clocking8.1 Operating Conditions 8.2 Electrical Specifications 8.3 Power Consumption SpecificationsPower and Clocking Table 8-2. Absolute Maximum RatingsPower and Clocking Table 8-3. Power Consumption Specifications Sheet 1 of8.4 Oscillator Electrical Specifications 8.4.1 32.768 kHz Oscillator SpecificationsPower and Clocking Table 8-3. Power Consumption Specifications Sheet 2 of8.4.2 3.6864 MHz Oscillator Specifications Power and ClockingTable 8-4. 32.768 kHz Oscillator Specifications Sheet 2 of Table 8-5. 3.6864 MHz Oscillator Specifications8.5 Reset and Power AC Timing Specifications 8.5.1 Power Supply ConnectivityPower and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 1 ofPXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 2 of PXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 3 of PXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 4 of PXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 5 of 8.5.2 Power On Timing Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 6 of 8-118.5.3 Hardware Reset Timing Power and ClockingFigure 8-1. Power-On Reset Timing JTAG PINS8.5.4 Watchdog Reset Timing 8.5.5 GPIO Reset TimingPower and Clocking Figure 8-2. Hardware Reset Timing8.5.6 Sleep Mode Timing Power and ClockingTable 8-9. GPIO Reset Timing Specifications GPx PWREN VCC nVDDFAULT nRESETOUT8.6 Memory Bus and PCMCIA AC Specifications Power and ClockingTable 8-10. Sleep Mode Timing Specifications Sheet 2 of 8-15PXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-12. Variable Latency I/O Interface AC Specifications Power and Clocking Table 8-14. Synchronous Memory Interface AC Specifications 3.38-17 PXA250 and PXA210 Applications Processors Design GuidePower and Clocking PXA250 and PXA210 Applications Processors Design GuidePower and Clocking Table 8-16. Variable Latency I/O Interface AC Specifications 2.58-19 PXA250 and PXA210 Applications Processors Design Guide8.7 Example Form Factor Reference Design Power Delivery Example 8.7.1 Power SystemPower and Clocking Table 8-18. Synchronous Memory Interface AC Specifications 2.58-21 8.7.1.1 Power System ConfigurationPower and Clocking 8.7.2 CORE Power 8.7.3 PLL PowerPower and Clocking Figure 8-5. Example Form Factor Reference Design Power System Design8.7.4 I/O 3.3 V Power 8.7.5 Peripheral 5.5 V PowerPower and Clocking 8-23Power and Clocking PXA250 and PXA210 Applications Processors Design Guide9.2 Schematics JTAG/Debug Port9.1 Description Figure 9-1. JTAG/Debug Port Wiring DiagramPXA250 and PXA210 Applications Processors Design Guide 9.3 LayoutJTAG/Debug Port PXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications ProcessorMigration A.1 SA-1110 Hardware Migration Issues A.1.2 Signal ChangesA.1.1 Hardware Compatibility Table A-1. PXA250 Boot Select Options Sheet 1 ofTable A-1. PXA250 Boot Select Options Sheet 2 of Figure A-1. Write Enable Control PinsSA-1110 PXA250A.1.3 Power Delivery A.1.4 PackageA.1.5 Clocks SA-1110/Applications Processor MigrationA.2 SA-1110 to PXA250 Software Migration Issues A.1.6 UCB1300SA-1110/Applications Processor Migration PXA250 and PXA210 Applications Processors Design GuideA.2.4 Configuration registers A.2.1 Software CompatibilityA.2.2 Address space A.2.3 Page Table ChangesA.3 Using New PXA250 Features A.2.5 DMASA-1110/Applications Processor Migration PXA250 and PXA210 Applications Processors Design GuideA.3.4 Other features A.3.1 Intel XScale MicroarchitectureA.3.2 Debugging A.3.3 Cache AttributesPXA250 and PXA210 Applications Processors Design Guide A.3.5 ConclusionSA-1110/Applications Processor Migration PXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications Processor MigrationA-10 Schematic Diagrams B.2 Schematic DiagramsExample Form Factor Reference Design B.1 NotesPage Address and Data Buses Pg.2Intel PXA250 Processor RESET Pg.3Intel PXA250 Processor Capacitors for CoreSDRAM Bank Addressing SYSTEM CONFIGURATION REGISTERSDRAM Flash Memory Resistor StrataFlashSynchronous StrataFlashBuffer Board ControlRegister CPLDTransceivers 74LVCH16245A74LVCH16245A 74LVCH16245AAudio CODEC Audio AmpUCB1400 Modem / AudioIrDA Transceiver Headset JackMicrophone SpeakerMomentary Switches Three Position SwitchBase Station Connector Compact Flash Type II SocketConnector JTAG ICE ConnectorSD Socket RadioBattery Connector Battery Charger5.5 Volt Supply Processor Core Voltage SupplyLCD CPLD Note Onboard Back Light InverterLCD Power Sharp LCD ConnectorConnector Toshiba LCD ConnectorExpansion ExpansionHeader HeaderRevision Tracking Changes PXA250 and PXA210 Applications Processors Design Guide Example Form Factor Reference Design Schematic DiagramsB-18 Schematic Diagram C.1 Schematic DiagramBBPXA2xx Development Baseboard PXA250 and PXA210 Applications Processors Design GuideTable of Contents BBPXA2xxPage Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page PXA250 and PXA210 Applications Processors Design Guide BBPXA2xx Development Baseboard Schematic DiagramC-40 PXA250 Processor Card Schematic DiagramD.1 Schematic Diagram PXA250 and PXA210 Applications Processors Design Guide7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER TABLE OF CONTENTSDCPXA250 Processor Card 32-bit version Page Page Page Page Page Page Page Page Page Page PXA210 Processor Card Schematic E.1 Schematic DiagramDiagram The DCPXA210 processor card schematic is on the following pagesDCPXA210 Processor Card 16-bit version TABLE OF CONTENTSCONNECTOR MEMORY and I/O SIGNALS PAGEPage Page Page Page Page Page Page Page Page Page Page Page PXA210 Processor Card Schematic Diagram PXA250 and PXA210 Applications Processors Design Guide