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Intel PXA250 and PXA210 manual Active TFT Displays, LCD Display Controller

Models: PXA250 and PXA210

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Figure 3-5. Passive Color Dual Panel Displays Typical Connection

LCD Display Controller

Figure 3-5. Passive Color Dual Panel Displays Typical Connection

PXA250 Processor

L_DD0	DU_0
L_DD1	DU_1
L_DD2	DU_2
L_DD3	DU_3
L_DD4	DU_4
L_DD5 - Top left Blue for upper panel	DU_5
L_DD6 - Top left Green for upper panel	DU_6
L_DD7 - Top left Red for upper panel	DU_7
L_PCLK	Pixel_Clock
L_LCLK	Line_Clock
L_FCLK	Frame_Clock
L_BIAS	Bias
L_DD8	DL_0
L_DD9	DL_1
L_DD10	DL_2
L_DD11	DL_3
L_DD12	DL_4
L_DD13 - Top left Blue for lower panel	DL_5
L_DD14 - Top left Green for lower panel	DL_6
L_DD15 - Top left Red for lower panel	DL_7

Upper Panel

LCD Display

Lower Panel

3.3Active (TFT) Displays

Because data is sent to the panel as raw 16-bit pixel data, active displays require16 data pins in order to transfer the pixel data from the controller. All 16 data lines are also required to drive one pixel value. The 16 bits of data describe the intensity level of the red, green and blue for each pixel. Typically, this is formatted as 5 bits for red, 6 bits for green and 5 bits for blue, but this can vary by display and is controlled by the software writing to the frame buffer. Refer to the display datasheet to ensure that the correct the PXA250 applications processor LCD data lines are connected to the correct LCD panel data lines.

Many active displays actually have more than 16 data lines - usually 18 (6 of each color). For these panels it is recommended that the most significant lines of the panel lines are connected to the data lines from the PXA250 applications processor. This maintains the panel’s full range of colors but increases the granularity of the color spectrum with an insufficient number of data lines. All unused panel data lines can be tied either high or low. Other options include tying the LSB of red and blue to the next bit, R1 or B1.

For active displays, connect the pins described in Table 3-3between the PXA250 applications processor and the LCD panel.

PXA250 and PXA210 Applications Processor Design Guide

3-5

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Intel manual Active TFT Displays, LCD Display Controller, PXA250 and PXA210 Applications Processor Design Guide

Contents

Intel PXA250 and PXA210 Applications Processors Design GuideFebruary Order NumberPXA250 and PXA210 Applications Processors Design Guide Contents ContentsUSB Interface PXA250 and PXA210 Applications Processors Design GuideMultiMediaCard MMC ContentsAC97 PXA250 and PXA210 Applications Processors Design GuideExample Form Factor Reference Design Schematic Diagrams ContentsPXA250 and PXA210 Applications Processors Design Guide Tables FiguresContents PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide ContentsPXA250 and PXA210 Applications Processors Design Guide Contents1.1 Functional Overview IntroductionRevision History Table 1-2. Related Documentation1.2.1 Package Introduction 1.2 Package InformationFigure 1-1. Applications Processor Block Diagram OS TimerPXA250 and PXA210 Applications Processors Design Guide IntroductionTable 1-3. Signal Pin Descriptions Sheet 1 of 1.2.2 Signal Pin DescriptionsIntroduction PXA250 and PXA210 Applications Processors Design GuideIntroduction Table 1-3. Signal Pin Descriptions Sheet 2 ofPXA250 and PXA210 Applications Processors Design Guide Introduction Table 1-3. Signal Pin Descriptions Sheet 3 ofPXA250 and PXA210 Applications Processors Design Guide Introduction Table 1-3. Signal Pin Descriptions Sheet 4 ofPXA250 and PXA210 Applications Processors Design Guide BOOTSEL20 Description Table 1-3. Signal Pin Descriptions Sheet 5 ofIntroduction PXA250 and PXA210 Applications Processors Design GuideIntroduction Table 1-3. Signal Pin Descriptions Sheet 6 ofPXA250 and PXA210 Applications Processors Design Guide Introduction Table 1-3. Signal Pin Descriptions Sheet 7 ofPXA250 and PXA210 Applications Processors Design Guide Figure 1-2. PXA250 Applications Processor Introduction1-11 PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Introduction1-13 IntroductionPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide IntroductionFigure 1-3. PXA210 Applications Processor Introduction1-15 PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Introduction1-17 IntroductionPXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide Introduction2.1 Overview System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide System Memory Interface Figure 2-1. General Memory Interface ConfigurationPXA250 and PXA210 Applications Processors Design Guide Card Memory Interface2.2 SDRAM Interface 2.3 SDRAM memory wiring diagramSystem Memory Interface Table 2-1. Memory Address MapFigure 2-2. SDRAM Memory System Example System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide System Memory Interface 2.4 SDRAM SupportTable 2-2. SDRAM Memory Types Supported by the Applications Processor PXA250 and PXA210 Applications Processors Design GuideSystem Memory Interface 2.5 SDRAM Address MappingTable 2-3. Normal Mode Memory Address Mapping PXA250 and PXA210 Applications Processors Design Guide2.6.1 Overview 2.6 Static MemorySystem Memory Interface PXA250 and PXA210 Applications Processors Design GuideTable 2-5. Valid Booting Configurations Based on Package Type 2.6.2 Boot Time DefaultsTable 2-6. BOOTSEL Definitions Sheet 1 of System Memory Interface2.6.4 Variable Latency I/O Interface Overview 2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory OptionsTable 2-6. BOOTSEL Definitions Sheet 2 of System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide System Memory Interfacememlk nCS0System Memory Interface 2.6.5 External Logic for PCMCIA Implementation2-11 PXA250 and PXA210 Applications Processors Design Guide System Memory InterfacePXA250 Applications Processor Socket2-13 System Memory InterfacePXA250 SocketSystem Memory Interface 2.6.6 DMA / Companion Chip InterfaceConnect a companion chip to the applications processor via Alternate Bus Master Mode Variable Latency I/O Flow through DMAMemory PXA250Controller PXA250System Memory Interface PXA250Figure 2-7. Variable Latency I/O EXTERNAL SYSTEM2.7.1 System Memory Topologies Min and Max Simulated Loading 2.7 System Memory Layout GuidelinesCS, CKE, DQM CLK, MA CS, CKE, DQM CLK, MATable 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals 2.7.2 System Memory Recommended Trace LengthsSystem Memory Interface Figure 2-11. MD maximum loading topology3.1 LCD Display Overview LCD Display Controller3.2 Passive DSTN Displays Table 3-1. LCD Controller Data Pin Utilization Sheet 1 ofTable 3-2. Passive Display Pins Required 3.2.1 Typical Connections for Passive Panel Displays3.2.1.1 Passive Monochrome Single Panel Displays LCD Display Controller3.2.1.3 Passive Monochrome Dual Panel Displays 3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel DataLCD Display Controller PXA250 and PXA210 Applications Processor Design Guide3.2.1.5 Passive Color Dual Panel Displays 3.2.1.4 Passive Color Single Panel DisplaysLCD Display Controller Figure 3-3. Passive Monochrome Dual Panel Displays Typical ConnectionLCD Display Controller 3.3 Active TFT DisplaysFigure 3-5. Passive Color Dual Panel Displays Typical Connection PXA250 and PXA210 Applications Processor Design GuideTable 3-3. Active Display Pins Required 3.3.1 Typical connections for Active Panel DisplaysLCD Display Controller PXA250 and PXA210 Applications Processor Design GuideLCD Display Controller 3.4 PXA250 PinoutFigure 3-6. Active Color Display Typical Connection Table 3-4. PXA250 LCD Controller Ball Positions Sheet 1 of3.5 Additional Design Considerations 3.5.3 Signal Routing and Buffering3.5.1 Contrast Voltage 3.5.2 Backlight InverterLCD Display Controller 3.5.4 Panel ConnectorPXA250 and PXA210 Applications Processor Design Guide PXA250 and PXA210 Applications Processor Design Guide LCD Display Controller4.1.1 Operation if GPIOn and GPIOx are Different Pins 4.1 Self Powered DeviceUSB Interface Figure 4-1. Self Powered Device4.1.2 Operation if GPIOn and GPIOx are the Same Pin 4.2 Bus Powered DeviceUSB Interface PXA250 and PXA210 Applications Processors Design Guide5.1.1 Signal Description 5.1 SchematicsMultiMediaCard MMC Table 5-1. MMC Signal DescriptionTable 5-2. SDCard Socket Signals 5.1.2 How to WireMultiMediaCard MMC Table 5-3. MMC Controller Supported Sockets and DevicesMultiMediaCard MMC Figure 5-1. Applications Processor MMC and SDCard Signal Connections5.1.2.2 MMC Socket 5.1.2.1 SDCard SocketMultiMediaCard MMC PXA250 and PXA210 Applications Processors Design GuideMultiMediaCard MMC 5.1.3 Simplified Schematic5.1.4 Pull-up and Pull-down 5.2 Utilized FeaturesMultiMediaCard MMC Table 5-4. SDCard Pull-up and Pull-down ResistorsAC97 6.1 SchematicsFigure 6-1. AC97 connection PXA250 and PXA210 Applications Processors Design GuideAC97 6.2 LayoutPXA250 and PXA210 Applications Processors Design Guide 7.1.1 Signal Description 7.1 SchematicsTable 7-1. I2C Signal Description PXA250 and PXA210 Applications Processors Design Guide7.1.3 Other Uses of I2C 7.1.2 Digital-to-Analog Converter DACFigure 7-1. Linear Technology DAC with I2C Interface PXA250 and PXA210 Applications Processors Design GuideFigure 7-2. Using an Analog Switch to Allow a Second CF Card 7.1.4 Pull-Ups and Pull-DownsFigure 7-3. I2C Pull-Ups and Pull-Downs PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide 7.2 Utilized Features8.1 Operating Conditions Power and ClockingPXA250 and PXA210 Applications Processors Design Guide 8.3 Power Consumption Specifications 8.2 Electrical SpecificationsPower and Clocking Table 8-2. Absolute Maximum RatingsTable 8-3. Power Consumption Specifications Sheet 1 of Power and Clocking8.4.1 32.768 kHz Oscillator Specifications 8.4 Oscillator Electrical SpecificationsPower and Clocking Table 8-3. Power Consumption Specifications Sheet 2 ofPower and Clocking 8.4.2 3.6864 MHz Oscillator SpecificationsTable 8-4. 32.768 kHz Oscillator Specifications Sheet 2 of Table 8-5. 3.6864 MHz Oscillator Specifications8.5.1 Power Supply Connectivity 8.5 Reset and Power AC Timing SpecificationsPower and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 1 ofTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 2 of Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 3 of Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 4 of Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 5 of Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Power and Clocking 8.5.2 Power On TimingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 6 of 8-11Power and Clocking 8.5.3 Hardware Reset TimingFigure 8-1. Power-On Reset Timing JTAG PINS8.5.5 GPIO Reset Timing 8.5.4 Watchdog Reset TimingPower and Clocking Figure 8-2. Hardware Reset TimingPower and Clocking 8.5.6 Sleep Mode TimingTable 8-9. GPIO Reset Timing Specifications GPx PWREN VCC nVDDFAULT nRESETOUTPower and Clocking 8.6 Memory Bus and PCMCIA AC SpecificationsTable 8-10. Sleep Mode Timing Specifications Sheet 2 of 8-15Table 8-12. Variable Latency I/O Interface AC Specifications Power and ClockingPXA250 and PXA210 Applications Processors Design Guide Table 8-14. Synchronous Memory Interface AC Specifications 3.3 Power and Clocking8-17 PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-16. Variable Latency I/O Interface AC Specifications 2.5 Power and Clocking8-19 PXA250 and PXA210 Applications Processors Design Guide8.7.1 Power System 8.7 Example Form Factor Reference Design Power Delivery ExamplePower and Clocking Table 8-18. Synchronous Memory Interface AC Specifications 2.5Power and Clocking 8.7.1.1 Power System Configuration8-21 8.7.3 PLL Power 8.7.2 CORE PowerPower and Clocking Figure 8-5. Example Form Factor Reference Design Power System Design8.7.5 Peripheral 5.5 V Power 8.7.4 I/O 3.3 V PowerPower and Clocking 8-23PXA250 and PXA210 Applications Processors Design Guide Power and ClockingJTAG/Debug Port 9.2 Schematics9.1 Description Figure 9-1. JTAG/Debug Port Wiring DiagramJTAG/Debug Port 9.3 LayoutPXA250 and PXA210 Applications Processors Design Guide Migration SA-1110/Applications ProcessorPXA250 and PXA210 Applications Processors Design Guide A.1.2 Signal Changes A.1 SA-1110 Hardware Migration IssuesA.1.1 Hardware Compatibility Table A-1. PXA250 Boot Select Options Sheet 1 ofFigure A-1. Write Enable Control Pins Table A-1. PXA250 Boot Select Options Sheet 2 ofSA-1110 PXA250A.1.4 Package A.1.3 Power DeliveryA.1.5 Clocks SA-1110/Applications Processor MigrationA.1.6 UCB1300 A.2 SA-1110 to PXA250 Software Migration IssuesSA-1110/Applications Processor Migration PXA250 and PXA210 Applications Processors Design GuideA.2.1 Software Compatibility A.2.4 Configuration registersA.2.2 Address space A.2.3 Page Table ChangesA.2.5 DMA A.3 Using New PXA250 FeaturesSA-1110/Applications Processor Migration PXA250 and PXA210 Applications Processors Design GuideA.3.1 Intel XScale Microarchitecture A.3.4 Other featuresA.3.2 Debugging A.3.3 Cache AttributesSA-1110/Applications Processor Migration A.3.5 ConclusionPXA250 and PXA210 Applications Processors Design Guide A-10 SA-1110/Applications Processor MigrationPXA250 and PXA210 Applications Processors Design Guide B.2 Schematic Diagrams Schematic DiagramsExample Form Factor Reference Design B.1 NotesPage Intel PXA250 Processor Pg.2Address and Data Buses Pg.3 RESETIntel PXA250 Processor Capacitors for CoreSDRAM SYSTEM CONFIGURATION REGISTERSDRAM Bank Addressing Resistor StrataFlash Flash MemorySynchronous StrataFlashBoard Control BufferRegister CPLD74LVCH16245A Transceivers74LVCH16245A 74LVCH16245AAudio Amp Audio CODECUCB1400 Modem / AudioHeadset Jack IrDA TransceiverMicrophone SpeakerThree Position Switch Momentary SwitchesBase Station Connector Compact Flash Type II SocketJTAG ICE Connector ConnectorSD Socket RadioBattery Charger Battery Connector5.5 Volt Supply Processor Core Voltage SupplyNote On LCD CPLDboard Back Light InverterSharp LCD Connector LCD PowerConnector Toshiba LCD ConnectorExpansion ExpansionHeader HeaderRevision Tracking Changes B-18 Example Form Factor Reference Design Schematic DiagramsPXA250 and PXA210 Applications Processors Design Guide C.1 Schematic Diagram Schematic DiagramBBPXA2xx Development Baseboard PXA250 and PXA210 Applications Processors Design GuideBBPXA2xx Table of ContentsPage Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page C-40 BBPXA2xx Development Baseboard Schematic DiagramPXA250 and PXA210 Applications Processors Design Guide Diagram PXA250 Processor Card SchematicD.1 Schematic Diagram PXA250 and PXA210 Applications Processors Design GuideDCPXA250 Processor Card 32-bit version TABLE OF CONTENTS7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER Page Page Page Page Page Page Page Page Page Page E.1 Schematic Diagram PXA210 Processor Card SchematicDiagram The DCPXA210 processor card schematic is on the following pagesTABLE OF CONTENTS DCPXA210 Processor Card 16-bit versionCONNECTOR MEMORY and I/O SIGNALS PAGEPage Page Page Page Page Page Page Page Page Page Page Page PXA250 and PXA210 Applications Processors Design Guide PXA210 Processor Card Schematic Diagram