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Intel PXA250 and PXA210 manual JTAG/Debug Port, Description, Schematics

Models: PXA250 and PXA210

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JTAG/Debug Port

JTAG/Debug Port

9

9.1Description

The JTAG/Debug port is essentially several shift registers, with the destination controlled by the TMS pin and data I/O with TDI/TDO. nTRST provides initialization of the test logic. JTAG is testable via the IEEE 1149.1. Many use JTAG to control the address/data bus for Flash programming. JTAG is also a hardware debug port.

9.2Schematics

All JTAG pins, except for nTRST and TCK, are directly connected. TCK is not driven internally and so you must add an external pull-up or pull-down resistor. Intel recommends adding a 1.5 k pull-down resistor to TCK. nTRST must be asserted during power-on. Asserting nRESET or nTRST must not cause the other reset signal to assert. Also, use an external pull-up resistor on nTRST to prevent spurious resets of the JTAG port when disconnected. The circuit in Figure 9-1drives nTRST. It uses a reset IC on nTRST to ensure that nTRST is reset at power-on. nRESET must be directly connected to the CPU nRESET. Do not connect pins 17 and 19 – they are special purpose functions and not used.

Figure 9-1. JTAG/Debug Port Wiring Diagram

3.3 V

	RESET	MR		1	2
nTRST	RESET	MR		3	4
nTRST	MAX823			3	4
	MAX823		TDI	5	6
			TDI	5	6
			TMS	7	8
	TCK			9	10
		1.5K	GND	11	12
			TDO	13	14
nRESET				15	16
				17	18
				19	20

If you are not utilizing either JTAG or the hardware debug functions, it is highly recommended that you design in a JTAG/debug port on your system anyway. This greatly facilitates board debug, startup, and software development. During final production you would not have to populate the JTAG connector.

PXA250 and PXA210 Applications Processors Design Guide

9-1

Image 93

Intel PXA250 and PXA210 manual Description, Schematics, 1. JTAG/Debug Port Wiring Diagram

Contents

Intel PXA250 and PXA210 Applications Processors Design GuideFebruary Order NumberPXA250 and PXA210 Applications Processors Design Guide Contents ContentsUSB Interface PXA250 and PXA210 Applications Processors Design GuideMultiMediaCard MMC ContentsAC97 PXA250 and PXA210 Applications Processors Design GuideContents Example Form Factor Reference Design Schematic DiagramsPXA250 and PXA210 Applications Processors Design Guide Tables FiguresContents PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide ContentsPXA250 and PXA210 Applications Processors Design Guide Contents1.1 Functional Overview IntroductionRevision History Table 1-2. Related Documentation1.2.1 Package Introduction 1.2 Package InformationFigure 1-1. Applications Processor Block Diagram OS TimerPXA250 and PXA210 Applications Processors Design Guide IntroductionTable 1-3. Signal Pin Descriptions Sheet 1 of 1.2.2 Signal Pin DescriptionsIntroduction PXA250 and PXA210 Applications Processors Design GuideTable 1-3. Signal Pin Descriptions Sheet 2 of IntroductionPXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 3 of IntroductionPXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 4 of IntroductionPXA250 and PXA210 Applications Processors Design Guide BOOTSEL20 Description Table 1-3. Signal Pin Descriptions Sheet 5 ofIntroduction PXA250 and PXA210 Applications Processors Design GuideTable 1-3. Signal Pin Descriptions Sheet 6 of IntroductionPXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 7 of IntroductionPXA250 and PXA210 Applications Processors Design Guide Figure 1-2. PXA250 Applications Processor Introduction1-11 PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide IntroductionIntroduction 1-13PXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide IntroductionFigure 1-3. PXA210 Applications Processor Introduction1-15 PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide IntroductionIntroduction 1-17PXA250 and PXA210 Applications Processors Design Guide PXA250 and PXA210 Applications Processors Design Guide IntroductionSystem Memory Interface 2.1 OverviewPXA250 and PXA210 Applications Processors Design Guide System Memory Interface Figure 2-1. General Memory Interface ConfigurationPXA250 and PXA210 Applications Processors Design Guide Card Memory Interface2.2 SDRAM Interface 2.3 SDRAM memory wiring diagramSystem Memory Interface Table 2-1. Memory Address MapSystem Memory Interface Figure 2-2. SDRAM Memory System ExamplePXA250 and PXA210 Applications Processors Design Guide System Memory Interface 2.4 SDRAM SupportTable 2-2. SDRAM Memory Types Supported by the Applications Processor PXA250 and PXA210 Applications Processors Design GuideSystem Memory Interface 2.5 SDRAM Address MappingTable 2-3. Normal Mode Memory Address Mapping PXA250 and PXA210 Applications Processors Design Guide2.6.1 Overview 2.6 Static MemorySystem Memory Interface PXA250 and PXA210 Applications Processors Design GuideTable 2-5. Valid Booting Configurations Based on Package Type 2.6.2 Boot Time DefaultsTable 2-6. BOOTSEL Definitions Sheet 1 of System Memory Interface2.6.4 Variable Latency I/O Interface Overview 2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory OptionsTable 2-6. BOOTSEL Definitions Sheet 2 of System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide System Memory Interfacememlk nCS02.6.5 External Logic for PCMCIA Implementation System Memory Interface2-11 PXA250 and PXA210 Applications Processors Design Guide System Memory InterfacePXA250 Applications Processor Socket2-13 System Memory InterfacePXA250 SocketSystem Memory Interface 2.6.6 DMA / Companion Chip InterfaceConnect a companion chip to the applications processor via Alternate Bus Master Mode Variable Latency I/O Flow through DMAMemory PXA250Controller PXA250System Memory Interface PXA250Figure 2-7. Variable Latency I/O EXTERNAL SYSTEM2.7.1 System Memory Topologies Min and Max Simulated Loading 2.7 System Memory Layout GuidelinesCS, CKE, DQM CLK, MA CS, CKE, DQM CLK, MATable 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals 2.7.2 System Memory Recommended Trace LengthsSystem Memory Interface Figure 2-11. MD maximum loading topology3.1 LCD Display Overview LCD Display Controller3.2 Passive DSTN Displays Table 3-1. LCD Controller Data Pin Utilization Sheet 1 ofTable 3-2. Passive Display Pins Required 3.2.1 Typical Connections for Passive Panel Displays3.2.1.1 Passive Monochrome Single Panel Displays LCD Display Controller3.2.1.3 Passive Monochrome Dual Panel Displays 3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel DataLCD Display Controller PXA250 and PXA210 Applications Processor Design Guide3.2.1.5 Passive Color Dual Panel Displays 3.2.1.4 Passive Color Single Panel DisplaysLCD Display Controller Figure 3-3. Passive Monochrome Dual Panel Displays Typical ConnectionLCD Display Controller 3.3 Active TFT DisplaysFigure 3-5. Passive Color Dual Panel Displays Typical Connection PXA250 and PXA210 Applications Processor Design GuideTable 3-3. Active Display Pins Required 3.3.1 Typical connections for Active Panel DisplaysLCD Display Controller PXA250 and PXA210 Applications Processor Design GuideLCD Display Controller 3.4 PXA250 PinoutFigure 3-6. Active Color Display Typical Connection Table 3-4. PXA250 LCD Controller Ball Positions Sheet 1 of3.5 Additional Design Considerations 3.5.3 Signal Routing and Buffering3.5.1 Contrast Voltage 3.5.2 Backlight Inverter3.5.4 Panel Connector LCD Display ControllerPXA250 and PXA210 Applications Processor Design Guide PXA250 and PXA210 Applications Processor Design Guide LCD Display Controller4.1.1 Operation if GPIOn and GPIOx are Different Pins 4.1 Self Powered DeviceUSB Interface Figure 4-1. Self Powered Device4.1.2 Operation if GPIOn and GPIOx are the Same Pin 4.2 Bus Powered DeviceUSB Interface PXA250 and PXA210 Applications Processors Design Guide5.1.1 Signal Description 5.1 SchematicsMultiMediaCard MMC Table 5-1. MMC Signal DescriptionTable 5-2. SDCard Socket Signals 5.1.2 How to WireMultiMediaCard MMC Table 5-3. MMC Controller Supported Sockets and DevicesMultiMediaCard MMC Figure 5-1. Applications Processor MMC and SDCard Signal Connections5.1.2.2 MMC Socket 5.1.2.1 SDCard SocketMultiMediaCard MMC PXA250 and PXA210 Applications Processors Design GuideMultiMediaCard MMC 5.1.3 Simplified Schematic5.1.4 Pull-up and Pull-down 5.2 Utilized FeaturesMultiMediaCard MMC Table 5-4. SDCard Pull-up and Pull-down ResistorsAC97 6.1 SchematicsFigure 6-1. AC97 connection PXA250 and PXA210 Applications Processors Design Guide6.2 Layout AC97PXA250 and PXA210 Applications Processors Design Guide 7.1.1 Signal Description 7.1 SchematicsTable 7-1. I2C Signal Description PXA250 and PXA210 Applications Processors Design Guide7.1.3 Other Uses of I2C 7.1.2 Digital-to-Analog Converter DACFigure 7-1. Linear Technology DAC with I2C Interface PXA250 and PXA210 Applications Processors Design GuideFigure 7-2. Using an Analog Switch to Allow a Second CF Card 7.1.4 Pull-Ups and Pull-DownsFigure 7-3. I2C Pull-Ups and Pull-Downs PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide 7.2 Utilized FeaturesPower and Clocking 8.1 Operating ConditionsPXA250 and PXA210 Applications Processors Design Guide 8.3 Power Consumption Specifications 8.2 Electrical SpecificationsPower and Clocking Table 8-2. Absolute Maximum RatingsTable 8-3. Power Consumption Specifications Sheet 1 of Power and Clocking8.4.1 32.768 kHz Oscillator Specifications 8.4 Oscillator Electrical SpecificationsPower and Clocking Table 8-3. Power Consumption Specifications Sheet 2 ofPower and Clocking 8.4.2 3.6864 MHz Oscillator SpecificationsTable 8-4. 32.768 kHz Oscillator Specifications Sheet 2 of Table 8-5. 3.6864 MHz Oscillator Specifications8.5.1 Power Supply Connectivity 8.5 Reset and Power AC Timing SpecificationsPower and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 1 ofPower and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 2 ofPXA250 and PXA210 Applications Processors Design Guide Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 3 ofPXA250 and PXA210 Applications Processors Design Guide Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 4 ofPXA250 and PXA210 Applications Processors Design Guide Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 5 ofPXA250 and PXA210 Applications Processors Design Guide Power and Clocking 8.5.2 Power On TimingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 6 of 8-11Power and Clocking 8.5.3 Hardware Reset TimingFigure 8-1. Power-On Reset Timing JTAG PINS8.5.5 GPIO Reset Timing 8.5.4 Watchdog Reset TimingPower and Clocking Figure 8-2. Hardware Reset TimingPower and Clocking 8.5.6 Sleep Mode TimingTable 8-9. GPIO Reset Timing Specifications GPx PWREN VCC nVDDFAULT nRESETOUTPower and Clocking 8.6 Memory Bus and PCMCIA AC SpecificationsTable 8-10. Sleep Mode Timing Specifications Sheet 2 of 8-15Power and Clocking Table 8-12. Variable Latency I/O Interface AC SpecificationsPXA250 and PXA210 Applications Processors Design Guide Table 8-14. Synchronous Memory Interface AC Specifications 3.3 Power and Clocking8-17 PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-16. Variable Latency I/O Interface AC Specifications 2.5 Power and Clocking8-19 PXA250 and PXA210 Applications Processors Design Guide8.7.1 Power System 8.7 Example Form Factor Reference Design Power Delivery ExamplePower and Clocking Table 8-18. Synchronous Memory Interface AC Specifications 2.58.7.1.1 Power System Configuration Power and Clocking8-21 8.7.3 PLL Power 8.7.2 CORE PowerPower and Clocking Figure 8-5. Example Form Factor Reference Design Power System Design8.7.5 Peripheral 5.5 V Power 8.7.4 I/O 3.3 V PowerPower and Clocking 8-23PXA250 and PXA210 Applications Processors Design Guide Power and ClockingJTAG/Debug Port 9.2 Schematics9.1 Description Figure 9-1. JTAG/Debug Port Wiring Diagram9.3 Layout JTAG/Debug PortPXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications Processor MigrationPXA250 and PXA210 Applications Processors Design Guide A.1.2 Signal Changes A.1 SA-1110 Hardware Migration IssuesA.1.1 Hardware Compatibility Table A-1. PXA250 Boot Select Options Sheet 1 ofFigure A-1. Write Enable Control Pins Table A-1. PXA250 Boot Select Options Sheet 2 ofSA-1110 PXA250A.1.4 Package A.1.3 Power DeliveryA.1.5 Clocks SA-1110/Applications Processor MigrationA.1.6 UCB1300 A.2 SA-1110 to PXA250 Software Migration IssuesSA-1110/Applications Processor Migration PXA250 and PXA210 Applications Processors Design GuideA.2.1 Software Compatibility A.2.4 Configuration registersA.2.2 Address space A.2.3 Page Table ChangesA.2.5 DMA A.3 Using New PXA250 FeaturesSA-1110/Applications Processor Migration PXA250 and PXA210 Applications Processors Design GuideA.3.1 Intel XScale Microarchitecture A.3.4 Other featuresA.3.2 Debugging A.3.3 Cache AttributesA.3.5 Conclusion SA-1110/Applications Processor MigrationPXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications Processor Migration A-10PXA250 and PXA210 Applications Processors Design Guide B.2 Schematic Diagrams Schematic DiagramsExample Form Factor Reference Design B.1 NotesPage Pg.2 Intel PXA250 ProcessorAddress and Data Buses Pg.3 RESETIntel PXA250 Processor Capacitors for CoreSYSTEM CONFIGURATION REGISTER SDRAMSDRAM Bank Addressing Resistor StrataFlash Flash MemorySynchronous StrataFlashBoard Control BufferRegister CPLD74LVCH16245A Transceivers74LVCH16245A 74LVCH16245AAudio Amp Audio CODECUCB1400 Modem / AudioHeadset Jack IrDA TransceiverMicrophone SpeakerThree Position Switch Momentary SwitchesBase Station Connector Compact Flash Type II SocketJTAG ICE Connector ConnectorSD Socket RadioBattery Charger Battery Connector5.5 Volt Supply Processor Core Voltage SupplyNote On LCD CPLDboard Back Light InverterSharp LCD Connector LCD PowerConnector Toshiba LCD ConnectorExpansion ExpansionHeader HeaderRevision Tracking Changes Example Form Factor Reference Design Schematic Diagrams B-18PXA250 and PXA210 Applications Processors Design Guide C.1 Schematic Diagram Schematic DiagramBBPXA2xx Development Baseboard PXA250 and PXA210 Applications Processors Design GuideBBPXA2xx Table of ContentsPage Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page BBPXA2xx Development Baseboard Schematic Diagram C-40PXA250 and PXA210 Applications Processors Design Guide Diagram PXA250 Processor Card SchematicD.1 Schematic Diagram PXA250 and PXA210 Applications Processors Design GuideTABLE OF CONTENTS DCPXA250 Processor Card 32-bit version7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER Page Page Page Page Page Page Page Page Page Page E.1 Schematic Diagram PXA210 Processor Card SchematicDiagram The DCPXA210 processor card schematic is on the following pagesTABLE OF CONTENTS DCPXA210 Processor Card 16-bit versionCONNECTOR MEMORY and I/O SIGNALS PAGEPage Page Page Page Page Page Page Page Page Page Page Page PXA250 and PXA210 Applications Processors Design Guide PXA210 Processor Card Schematic Diagram