Intel PXA250 and PXA210 Hardware Reset Timing, Power and Clocking, 1. Power-On Reset Timing, Vccn

Power and Clocking

Note: If Hardware Reset is entered during Sleep Mode, the proper power-supply stabilization times and nRESET timing requirements indicated in Table 8-7,“Power-On Timing Specifications” on page 8-12must be observed.

Figure 8-1. Power-On Reset Timing

	tR_VCCQ
VCCQ, PWR_EN	tR_VCCN
	tD_VCCN
VCCN	tR_VCC
VCC	tD_VCC
	tD_NTRST
nTRST
JTAG PINS	tD_JTAG
nRESET	tD_NRESET

nRESET_OUT tD_OUT

Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is deasserted or PXA250 enters Sleep Mode

Table 8-7. Power-On Timing Specifications

Symbol	Description	Min	Typical	Max
tR_VCCQ	VCCQ Rise / Stabilization time	0.01 ms	—	100 ms
tR_VCCN	VCCN Rise / Stabilization time	0.01 ms	—	100 ms
tR_VCC	VCC, PLL_VCC Rise / Stabilization time	0.01 ms	—	10 ms
tD_VCCN	Delay between VCCQ stable and VCCN applied	0 ms	—	—
tD_VCC	Delay from VCCN stable and VCC, PLL_VCC applied	0 ms	—	—
tD_NTRST	Delay between VCC, PLL_VCC stable and nTRST deasserted	50 ms	—	—
tD_JTAG	Delay between nTRST deasserted and JTAG pins active, with	0.03 ms	—	—
	nRESET asserted
tD_NRESET	Delay between VCC, PLL_VCC stable and nRESET	50 ms	—	—
	deasserted
tD_OUT	Delay between nRESET deasserted and nRESET_OUT	18.1 ms	—	18.2 ms
	deasserted

8.5.3Hardware Reset Timing

The timing sequences shown in Figure 8-2 “Hardware Reset Timing” assumes the power supplies are stable at the assertion of nRESET. If the power supplies are unstable, follow the timings indicated in Section 8.5.2, “Power On Timing” on page 11.

8-12 PXA250 and PXA210 Applications Processors Design Guide