8

 

 

7

 

6

 

 

 

5

 

4

 

 

 

3

 

2

 

 

1

 

 

 

Copyright 2002 Intel Corporation

J15

RCPT AMP

 

 

 

 

 

 

 

 

 

 

J16

RCPT AMP

 

 

 

Pg. 15

 

 

 

 

 

 

 

2

 

1

 

 

 

 

 

 

 

 

 

2

 

1

 

 

 

 

 

 

{6,10}

VX_A0

4

C1

3

VX_A1

{6,10}

 

 

 

 

{6,10}

VX_A0

4

C1

3

VX_A1

{6,10}

 

 

 

 

 

C2

C1

 

 

 

 

C2

C1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{6,10}

VX_A2

6

C2

5

VX_A3

{6,10}

 

 

 

 

{6,10}

VX_A2

6

C2

5

VX_A3

{6,10}

 

 

 

 

 

8

7

 

 

 

 

8

7

 

 

 

 

 

{7,10}

VX_A4

 

VX_A5

{7,10}

 

 

 

 

{7,10}

VX_A4

 

VX_A5

{7,10}

 

 

 

 

 

10

C3

9

 

 

 

 

10

C3

9

 

 

 

 

 

{7,10}

VX_A6

VX_A7

{7,10}

 

 

 

 

{7,10}

VX_A6

VX_A7

{7,10}

 

 

 

 

 

C4

C3

 

 

 

 

C4

C3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{7,10}

VX_A8

12

C4

11

VX_A9

{7,10}

 

 

 

 

{7,10}

VX_A8

12

C4

11

VX_A9

{7,10}

 

 

 

 

 

14

13

 

 

 

 

14

13

 

 

 

 

 

{7,10}

VX_A10

 

VX_A11

{7}

 

 

 

 

{7,10}

VX_A10

 

VX_A11

{7}

 

 

 

 

 

 

16

 

15

 

 

 

 

16

 

15

 

 

 

D

DC3P3V

 

{7}

VX_A12

 

VX_A13

{7}

 

 

DC3P3V

 

{7}

VX_A12

 

VX_A13

{7}

 

DC3P3V

D

 

18

 

17

 

 

 

18

 

17

 

 

 

{7}

VX_A14

 

VX_A15

{7}

DC3P3V

 

{7}

VX_A14

 

VX_A15

{7}

 

 

 

 

 

 

20

 

19

 

 

 

20

 

19

 

 

 

 

 

 

 

{7}

VX_A16

 

VX_A17

{7}

 

 

 

{7}

VX_A16

 

VX_A17

{7}

 

 

 

 

 

 

 

22

 

21

 

 

 

 

 

22

 

21

 

 

 

 

 

 

 

{7}

VX_A18

 

VX_A19

{7}

 

 

 

 

 

{7}

VX_A18

 

VX_A19

{7}

 

 

 

 

 

 

 

24

C5

23

 

 

 

 

 

24

C5

23

 

 

 

 

 

 

 

{7}

VX_A20

VX_A21

{7}

 

 

 

 

 

{7}

VX_A20

VX_A21

{7}

 

 

 

 

 

 

 

C6

C5

 

 

 

 

 

C6

C5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{7}

VX_A22

26

C6

25

VX_A23

{7}

 

 

 

 

 

{7}

VX_A22

26

C6

25

VX_A23

{7}

 

 

 

 

 

 

 

28

27

 

 

 

 

 

28

27

 

 

 

 

 

 

 

{7}

VX_A24

 

VX_A25

{7}

 

 

 

 

 

{7}

VX_A24

 

VX_A25

{7}

 

 

 

 

 

 

 

30

C7

29

 

 

 

 

 

30

C7

29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C8

 

C7

 

 

 

 

 

 

 

 

 

C8

 

C7

 

 

 

 

 

 

 

{7}

 

VX_nSDCS_0

32

C8

31

VX_nSDCS_2 {6}

 

 

 

 

{7}

VX_nSDCS_0

32

C8

31

VX_nSDCS_2

{6}

 

 

 

 

 

34

33

 

 

 

 

34

33

 

 

 

 

{7}

 

VX_nSDCAS

 

VX_DQM_3

{7}

 

 

 

 

{7}

VX_nSDCAS

 

VX_DQM_3

{7}

 

 

 

 

 

36

 

35

 

 

 

 

36

 

35

 

 

 

 

{7}

 

VX_nSDRAS

 

VX_DQM_2

{7}

 

 

 

 

{7}

VX_nSDRAS

 

VX_DQM_2

{7}

 

 

 

 

 

38

 

37

 

 

 

 

38

 

37

 

 

 

 

{3}

 

BOOT_SEL_0

 

VX_DQM_1

{7}

 

 

 

 

{3}

BOOT_SEL_0

 

VX_DQM_1

{7}

 

 

 

 

 

40

 

39

 

 

 

 

40

 

39

 

 

 

 

{2}

 

SA_SDCKE_0

 

VX_DQM_0

{7}

 

 

 

 

{2}

SA_SDCKE_0

 

VX_DQM_0

{7}

 

 

 

 

 

42

 

41

 

 

 

 

42

 

41

 

 

 

 

{3}

 

BOOT_SEL_1

 

 

 

 

 

 

 

{3}

BOOT_SEL_1

 

 

 

 

 

 

 

 

 

44

C9

43

 

 

 

 

 

 

44

C9

43

 

 

 

 

 

 

 

{6}

 

VX_SDCKE_1

SA_SDCLK_0

{2,5}

 

 

 

 

{6}

VX_SDCKE_1

SA_SDCLK_0

{2,5}

 

 

 

 

 

C10

C9

 

 

 

 

C10

C9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

46

C10

45

 

 

 

 

 

 

 

 

 

46

C10

45

 

 

 

 

 

 

 

 

 

 

 

48

47

 

 

 

 

 

 

 

 

 

48

47

 

 

 

 

 

 

 

{7}

VX_SDCLK_1

 

VX_SDCLK_2 {6}

 

 

 

 

{7}

VX_SDCLK_1

 

VX_SDCLK_2

{6}

 

 

 

 

50

C11

49

 

 

 

 

50

C11

49

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C12

 

C11

 

 

 

 

 

 

 

 

 

C12

 

C11

 

 

 

 

 

 

 

{2,6}

 

SA_RD_nWR

52

C12

51

MBREQ_CF_DETECT

{3,13}

 

{2,6}

 

SA_RD_nWR

52

C12

51

MBREQ_CF_DETECT

{3,13}

 

 

 

 

54

53

 

 

54

53

 

 

 

{4,13}

nGFX_PRESENT

 

MBGNT_CF_IRQ

{3,6}

 

{4,13}

nGFX_PRESENT

 

MBGNT_CF_IRQ

{3,6}

 

C

 

56

 

55

 

56

 

55

C

 

{6,10}

CF_IRQ_LVL2OE

 

DREQ_1

{11}

 

 

 

{6,10}

CF_IRQ_LVL2OE

 

DREQ_1

{11}

 

 

 

58

 

57

 

 

 

58

 

57

 

 

 

LCD_DC5V

 

nJTAG_TRST

 

VX_D1

{7,10}

 

LCD_DC5V

 

 

 

nJTAG_TRST

 

VX_D1

{7,10}

LCD_DC5V

 

 

 

60

 

59

 

 

 

 

60

 

59

 

 

{7,10}

VX_D0

 

VX_D3

{7,10}

 

 

 

{7,10}

VX_D0

 

VX_D3

{7,10}

 

 

 

 

62

 

61

 

 

 

 

62

 

61

 

 

 

 

 

{7,10}

VX_D2

 

VX_D5

{7,10}

 

 

 

 

{7,10}

VX_D2

 

VX_D5

{7,10}

 

 

 

 

 

64

C13

63

 

 

 

 

64

C13

63

 

 

 

 

 

{7,10}

VX_D4

VX_D7

{7,10}

 

 

LCD_DC5V

{7,10}

VX_D4

VX_D7

{7,10}

 

 

 

 

 

C14

C13

 

 

C14

C13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{7,10}

VX_D6

66

C14

65

VX_D9

{7,10}

 

 

 

 

{7,10}

VX_D6

66

C14

65

VX_D9

{7,10}

DC3P3V

 

 

 

 

68

67

 

 

 

 

68

67

 

 

 

 

{7,10}

VX_D8

 

VX_D11

{7,10}

 

DC3P3V

 

 

{7,10}

VX_D8

 

VX_D11

{7,10}

 

 

 

 

70

C15

69

 

 

 

70

C15

69

 

 

 

 

 

{7,10}

VX_D10

VX_D13

{7,10}

 

 

 

{7,10}

VX_D10

VX_D13

{7,10}

 

 

 

 

 

C16

C15

 

 

 

 

C16

C15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{7,10}

VX_D12

72

C16

71

VX_D15

{7,10}

 

 

 

 

{7,10}

VX_D12

72

C16

71

VX_D15

{7,10}

 

 

 

 

 

74

73

 

 

 

 

74

73

 

 

 

 

 

{7,10}

VX_D14

 

 

 

 

 

 

 

{7,10}

VX_D14

 

 

 

 

 

 

 

 

 

76

 

75

VX_D17

{7}

 

 

 

 

76

 

75

VX_D17

{7}

 

 

 

 

 

 

 

{7}

VX_D16

 

 

 

 

 

{7}

VX_D16

 

 

 

 

 

 

 

 

78

 

77

 

 

 

 

78

 

77

 

 

 

 

 

 

 

{7}

VX_D18

 

VX_D19

{7}

 

 

 

 

{7}

VX_D18

 

VX_D19

{7}

 

 

 

 

 

 

 

80

 

79

 

 

 

 

80

 

79

 

 

 

 

 

 

 

{7}

VX_D20

 

VX_D21

{7}

 

 

 

 

{7}

VX_D20

 

VX_D21

{7}

 

 

 

 

 

 

 

82

 

81

 

 

 

 

82

 

81

 

 

 

 

 

 

 

{7}

VX_D22

 

VX_D23

{7}

 

 

 

 

{7}

VX_D22

 

VX_D23

{7}

 

 

 

 

 

 

 

84

C17

83

 

 

 

 

84

C17

83

 

 

 

 

 

 

 

{7}

VX_D24

VX_D25

{7}

 

 

 

 

{7}

VX_D24

VX_D25

{7}

 

 

 

 

 

 

 

C18

C17

 

 

 

 

C18

C17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{7}

VX_D26

86

C18

85

VX_D27

{7}

 

 

 

 

{7}

VX_D26

86

C18

85

VX_D27

{7}

 

 

 

 

 

 

 

88

87

 

 

 

 

88

87

 

 

 

 

 

 

 

{7}

VX_D28

 

VX_D29

{7}

 

 

 

 

{7}

VX_D28

 

VX_D29

{7}

 

 

 

 

 

 

 

90

C19

89

 

 

 

 

90

C19

89

 

 

 

 

 

 

 

{7}

VX_D30

VX_D31

{7}

 

 

 

 

{7}

VX_D30

VX_D31

{7}

 

 

 

 

 

 

 

C20

C19

 

 

 

 

C20

C19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{4,13}

nNEP_PRESENT

92

C20

91

IN_PWR

{10,12}

DC3P3V

 

{4,13}

nNEP_PRESENT

92

C20

91

IN_PWR

{10,12}

 

 

 

 

94

93

 

94

93

 

 

 

 

 

{2}

SA_RDY

 

SA_nCS_5

{2,6}

 

 

 

{2}

SA_RDY

 

SA_nCS_5

{2,6}

 

 

B

 

 

96

 

95

 

 

 

 

96

 

95

 

B

DC3P3V

 

{7}

VX_nWE

 

SA_nCS_4

{2,6}

 

 

DC3P3V

 

{7}

VX_nWE

 

SA_nCS_4

{2,6}

DC3P3V

 

 

98

 

97

 

 

 

98

 

97

 

 

 

{6,7}

VX_nOE

 

SA_nCS_3

{2,6}

 

 

 

{6,7}

VX_nOE

 

SA_nCS_3

{2,6}

 

 

 

{13,14}

DC_15V

100

 

99

nNEP_REG_CS

{6,10}

 

{13,14}

DC_15V

100

 

99

nNEP_REG_CS {6,10}

 

 

 

{3,10,11}

nRESET_IN

102

 

101

nNEP_FLASH_CS

{6}

 

 

{3,10,11}

 

nRESET_IN

102

 

101

nNEP_FLASH_CS {6}

 

 

 

104

 

103

 

 

 

104

 

103

 

 

{3,6,11,13}

nRESET_OUT

C21

SA_nCS_0

{2,6}

 

 

{3,6,11,13}

nRESET_OUT

C21

SA_nCS_0

 

{2,6}

 

 

 

C22

C21

 

 

C22

C21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{6,10}

CF_GFX_RESET

106

C22

105

 

 

 

 

{6,10}

CF_GFX_RESET

106

C22

105

 

 

 

 

 

 

108

107

 

 

 

 

108

107

 

 

 

 

 

 

{3,10} GFX_IRQ_CF_BVD2

 

SYSCLK

{8,13}

 

 

{3,10} GFX_IRQ_CF_BVD2

 

SYSCLK

{8,13}

 

 

 

110

C23

109

 

 

110

C23

109

 

 

 

 

{13}

VDD_FAULT

 

 

 

 

 

{13}

VDD_FAULT

 

 

 

 

 

 

 

C24

C23

 

 

 

 

 

C24

C23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{3,10}

SA1111_IRQ_CF_BVD1

112

C24

111

SA_nPOE

{2,6}

 

 

{3,10}

SA1111_IRQ_CF_BVD1

112

C24

111

SA_nPOE

{2,6}

 

 

 

114

113

 

 

114

113

 

 

 

 

{10,12}

 

IN_PWR

 

SA_nPWE

{2,6}

 

 

 

{10,12}

 

IN_PWR

 

SA_nPWE

{2,6}

 

 

 

 

 

116

 

115

 

 

 

 

116

 

115

 

 

 

 

{2,6}

SA_nIOIS16

 

SA_nPIOW

{2,6}

 

 

 

{2,6}

 

SA_nIOIS16

 

SA_nPIOW

{2,6}

 

 

 

 

118

 

117

 

 

 

 

118

 

117

 

 

 

 

{2,6}

SA_nPWAIT

 

SA_nPIOR

{2,6}

 

 

 

{2,6}

 

SA_nPWAIT

 

SA_nPIOR

{2,6}

 

 

 

 

120

 

119

 

 

 

 

120

 

119

 

 

 

 

 

{2}

SA_PSKTSEL

 

SA_nPCE_1

{2,6}

 

 

 

 

{2}

SA_PSKTSEL

 

SA_nPCE_1 {2,6}

 

 

 

 

 

122

 

121

 

 

 

 

122

 

121

 

 

 

 

{2,6}

SA_nPREG

 

SA_nPCE_2

{2,6}

 

 

 

{2,6}

 

SA_nPREG

 

SA_nPCE_2 {2,6}

 

 

 

 

124

C25

123

 

 

 

 

124

C25

123

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C26

 

C25

 

 

 

 

 

 

 

 

 

C26

 

C25

 

 

 

 

 

 

 

 

{11}

DVAL_1

126

C26

125

SA_BT_RXD

{2,11}

 

 

 

{11}

DVAL_1

126

C26

125

SA_BT_RXD

{2,11}

 

 

 

 

 

128

127

 

 

 

128

127

 

 

 

 

 

{11}

DVAL_0

 

SA_BT_TXD

{2,11}

 

 

 

{11}

DVAL_0

 

SA_BT_TXD

{2,11}

 

 

 

 

 

130

C27

129

 

 

 

130

C27

129

 

 

 

 

 

{11}

DREQ_0

SWAP_FLASH {6}

 

 

 

 

{11}

DREQ_0

SWAP_FLASH

{6}

 

 

 

 

 

C28

C27

 

 

 

 

C28

C27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

{3,10}

GPIO_0

132

C28

131

SA_FF_TXD

{2,10}

 

 

 

{3,10}

GPIO_0

132

C28

131

SA_FF_TXD

{2,10}

 

 

 

 

 

134

133

 

 

 

134

133

 

 

A

 

{3,9}

USB_WAKE

 

SA_FF_RXD

{2,10}

 

 

{3,9}

 

USB_WAKE

 

SA_FF_RXD

{2,10}

 

A

 

136

 

135

 

 

 

136

 

135

 

 

 

{2,10,12}

SA_I2C_SDA

 

 

 

 

 

 

{2,10,12}

SA_I2C_SDA

 

 

 

 

 

 

 

 

138

 

137

nVBATT_LOW_IRQ

{3,12}

 

138

 

137

nVBATT_LOW_IRQ {3,12}

 

 

 

{2,10,12}

SA_I2C_SCL

 

 

{2,10,12}

SA_I2C_SCL

 

 

 

 

140

 

139

 

140

 

139

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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PXA250 Processor Reference Design

 

 

 

 

 

 

 

 

 

 

 

Expansion

 

 

 

 

 

 

 

 

 

 

 

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2.07

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Date:

Tuesday, February 05, 2002

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Page 120
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Intel PXA250 and PXA210 manual Expansion

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.