Power and Clocking

Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 2 of 6)

Pin

Pin

Alt_fn

Alt_fn

Alt_fn

Alt_fn

Signal Description and

Power

Count

1-(in)

2-(in)

1-(out)

2-(out)

Comments

Supply

 

 

 

 

 

 

 

 

 

DQM(1:0)

2

 

 

 

 

Main Memory Bus SDRAM byte

VCCN

 

 

 

 

selects

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

nSDCS(3:2)

2

 

 

 

 

Main Memory Bus SDRAM chip

VCCN

 

 

 

 

selects

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

nSDCS(1:0)

2

 

 

 

 

Main Memory Bus SDRAM chip

VCCN

 

 

 

 

selects

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDCKE(1:0)

2

 

 

 

 

Main Memory Bus SDRAM clock

VCCN

 

 

 

 

enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDCLK(2)

1

 

 

 

 

Main Memory Bus SDRAM clocks

VCCN

 

 

 

 

 

 

 

 

SDCLK(1:0)

2

 

 

 

 

Main Memory Bus SDRAM clocks

VCCN

 

 

 

 

 

 

 

 

RD/nWR

1

 

 

 

 

CC Steering Signal

VCCN

 

 

 

 

 

 

 

 

CS(0)

1

 

 

 

 

Static chip selects

VCCN

 

 

 

 

 

 

 

 

GP15

1

 

 

 

nCS_1

Active low chip select 1

VCCN

 

 

 

 

 

 

 

 

GP18

1

RDY

 

 

 

Ext. Bus Ready

VCCN

 

 

 

 

 

 

 

 

GP19

1

DREQ[1]

 

 

 

Ext. Bus Master Request

VCCN

 

 

 

 

 

 

 

 

GP20

1

DREQ[0]

 

 

 

Ext. Bus Master Request

VCCN

 

 

 

 

 

 

 

 

GP21

1

 

 

 

 

General Purpose I/O pin

VCCN

 

 

 

 

 

 

 

 

GP22

1

 

 

 

 

General Purpose I/O pin

VCCN

 

 

 

 

 

 

 

 

GP33

1

 

 

 

nCS[5]

Active low chip select 5

VCCN

 

 

 

 

 

 

 

 

GP48

1

 

 

 

nPOE

Output Enable for Card Space

VCCN

 

 

 

 

 

 

 

 

GP49

1

 

 

 

nPWE

Write Enable for Card Space

VCCN

 

 

 

 

 

 

 

 

GP50

1

 

 

 

nPIOR

I/O Read for Card Space

VCCN

 

 

 

 

 

 

 

 

GP51

1

 

 

 

nPIOW

I/O Write for Card Space

VCCN

 

 

 

 

 

 

 

 

GP52

1

 

 

 

nPCE[1]

Card Enable for Card Space

VCCN

 

 

 

 

 

 

 

 

GP53

1

 

 

 

nPCE[2]

Card Enable for Card Space

VCCN

 

 

 

 

 

 

 

MMCCLK

 

MMC CLock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GP54

1

 

 

MMCCLK

 

MMC CLock

VCCN

 

 

 

 

 

 

 

 

pSKTSEL

Socket Select for Card Space

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GP55

1

 

 

 

nPREG

Card Address bit 26

VCCN

 

 

 

 

 

 

 

 

GP56

1

nPWAIT

 

 

 

Wait signal for Card Space

VCCN

 

 

 

 

 

 

 

 

GP57

1

nIOIS16

 

 

 

Bus Width select for I/O Card

VCCN

 

 

 

Space

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GP78

1

 

 

 

nCS[2]

Active low chip select 2

VCCN

 

 

 

 

 

 

 

 

GP79

1

 

 

 

nCS[3]

Active low chip select 3

VCCN

 

 

 

 

 

 

 

 

GP80

1

 

 

 

nCS[4]

Active low chip select 4

VCCN

 

 

 

 

 

 

 

 

PXA250 and PXA210 Applications Processors Design Guide

8-7

Page 75
Image 75
Intel manual PXA250 and PXA210 Vccn vs. Vccq Sheet 2, Pin Altfn Signal Description Power Count, Out Comments Supply

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.