Intel PXA250 and PXA210 Typical Connections for Passive Panel Displays, LCD Display Controller

LCD Display Controller

Table 3-1. LCD Controller Data Pin Utilization (Sheet 2 of 2)

Color/	Single/	Double-Pixel
Monochrome			Screen Portion	Pins
	Dual Panel	Mode
Panel
Color	Dual	N/A	Top	L_DD<7:0>
			Bottom	L_DD<15:8>

NOTE: 1. Double pixel data mode (DPD)=1.

For passive displays, the pins described in Table 3-2are required connections between the PXA250 applications processor and your LCD panel.

Table 3-2. Passive Display Pins Required

PXA250 Pin	LCD Panel Pin	PIn Type1	Definition
			Data lines used to transmit either four or eight data values at a time to
			the LCD display. For monochrome displays, each pin value represents
L_DD	DU_x, DL_x	Output	a single pixel; for passive color, groupings of three pin values represent
			one pixel (red, green, and blue data values). Either the bottom four pins
			(L_DD<3:0>), the bottom 8 pins (L_DD<7:0>) or all 16 pixel data pins
			(L_DD<15:0>)will be used as shown in Table 3-1
L_PCLK	Pixel_Clock	Output	Pixel Clock - used by the LCD display to clock the pixel data into the
			line shift register.
			Line Clock - used by the LCD display to signal the end of a line of pixels
L_LCLK	Line_Clock	Output	that transfers the line data from the shift register to the screen and
			increment the line pointers.
L_FCLK	Frame_Clock	Output	Frame Clock - used by the LCD displays to signal the start of a new
			frame of pixels that resets the line pointers to the top of the screen.
			AC bias used to signal the LCD display to switch the polarity of the
L_BIAS	Bias	Output	power supplies to the row and column axis of the screen to counteract
			DC offset.
N/A	Vcon2	N/A	Contrast Voltage - Adjustable voltage input to LCD panel - external
			voltage circuitry is required (no pin available on PXA250).

NOTES:

1.“Pin Type” is in reference to the PXA250 applications processor. Therefore, outputs are pins that drive a signal from the processor to another device.

2.Vcon is a signal external to the PXA250 applications processor. Please refer to “Contrast Voltage” on page 8

3.2.1Typical Connections for Passive Panel Displays

The following diagrams are typical connections and serve a guide for designing systems which contain passive LCD displays. Panels differ on which is the panel’s lest significant bit (Refer to the LCD panel reference documentation for the lest significant bit.) Each figure indicates the top-left pixel (1,1) bit. While dual panels indicates the top-left pixel (1,n/2) of the upper and lower panels and color passive panels show the top-left-pixel color bits.

3.2.1.1Passive Monochrome Single Panel Displays

Figure 3-1is a typical single-panel-monochrome passive display connection.

3-2 PXA250 and PXA210 Applications Processor Design Guide