Intel PXA250 and PXA210 Watchdog Reset Timing, GPIO Reset Timing, Power and Clocking, nRESET

Power and Clocking

Figure 8-2. Hardware Reset Timing

		nRESET			tDHW_NRESET
		nRESET_OUT					tDHW_OUT
				tDHW_OUT_A
			Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted
			or PXA250 enters Sleep Mode
Table 8-8. Hardware Reset Timing Specifications
Symbol		Description			Min	Typical			Max
tDHW_NRESET	Minimum assertion time of nRESET				0.001 ms	—			—
tDHW_OUT_A	Delay between nRESET Asserted and nRESET_OUT Asserted				0 ms	—		0.001 ms
tDHW_OUT	Delay between nRESET deasserted and nRESET_OUT				18.1 ms	—		18.2 ms
	deasserted

8.5.4Watchdog Reset Timing

Watchdog Reset is an internally generated reset and therefore has no external pin dependencies. The nRESET_OUT pin is the only indicator of Watchdog Reset, and it stays asserted for tDHW_OUT. Refer to Figure 8-2, “Hardware Reset Timing” on page 8-13for more information.

8.5.5GPIO Reset Timing

GPIO Reset is generated externally. The pin used as the GPIO Reset is reconfigured as a standard GPIO after the reset propagates internally. Because the clock module is not reset by GPIO Reset, timing varies based on the frequency of the selected clock. Timing also varies in the Frequency Change Sequence (see Section 8.4.1, “32.768 kHz Oscillator Specifications” on page 4). Figure 8-3 “GPIO Reset Timing” shows the possible GPIO Reset timing.

Figure 8-3. GPIO Reset Timing

tA_GP[1]

GP[1]

nRESET_OUT

tDGP_OUT

tDGP_OUT_A

Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted or PXA250 enters Sleep Mode

PXA250 and PXA210 Applications Processors Design Guide 8-13