![2.6.5External Logic for PCMCIA Implementation](/images/new-backgrounds/89363/8936373x1.webp)
System Memory Interface
Table
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Symbol | Description |
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99.5 | 118.0 |
| 132.7 |
| 147.5 | 165.9 | Notes | ||
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tvlioDSW | MD(31:0), DQM(3:0) write data setup to | 10 | 8.5 |
| 7.5 |
| 6.8 | 6 | ns, 1 |
nPWE asserted |
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tvlioDSWH | MD(31:0), DQM(3:0) write data setup to | 20 | 17 |
| 15 |
| 13.6 | 12 | ns, 2 |
nPWE |
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tvlioDHW | MD(31:0), DQM(3:0) hold after nPWE | 10 | 8.5 |
| 7.5 |
| 6.8 | 6 | ns, 1 |
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tvlioDHR | MD(31:0) read data hold after nOE de- | 0 | 0 |
| 0 |
| 0 | 0 | ns |
asserted |
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tvlioRDYH | RDY hold after nOE, nPWE de- | 0 | 0 |
| 0 |
| 0 | 0 | ns |
asserted |
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tvlioNPWE | nPWE, nOE high time between beats of | 20 | 17 |
| 15 |
| 13.6 | 12 | ns, 2 |
write or read data |
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NOTES: |
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1.This number represents 1 MEMCLK period
2.This number represents 2 MEMCLK periods
2.6.5External Logic for PCMCIA Implementation
The PXA250 applications processor requires external glue logic to complete the PCMCIA socket interface. Figure
12and Figure
external registers to control the PCMCIA interface’s reset, power selection (VCC and VPP), and drive enables. These diagrams show the logical connections necessary to support hot insertion capability. For
Note: For 2.5 V VCCN, 5 V to 2.5 V level shifters are required.
Note: PCMCIA is only implemented on the PXA250 applications processor.
In the
PXA250 and PXA210 Applications Processors Design Guide |
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