Introduction
Table
Ball # | Signal | Ball # | Signal | Ball # | Signal |
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C6 | VCCQ | H12 | TCK | P2 | MA[19] |
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C7 | L_DD[2]/GPIO[60] | H13 | TMS | P3 | VCCN |
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C8 | VSSQ | H14 | GPIO[6] | P4 | MA[25] |
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C9 | BITCLK/GPIO[28] | H15 | TDI | P5 | MA[23] |
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C10 | VCCQ | H16 | TDO | P6 | MD[24] |
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C11 | VSSQ | J1 | MA[7] | P7 | MD[26] |
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C12 | USB_P | J2 | VSSN | P8 | MD[27] |
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C13 | VCCQ | J3 | MA[6] | P9 | nCS[2]/GPIO[78] |
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C14 | VSSQ | J4 | MD[18] | P10 | MD[29] |
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C15 | IRTXD/GPIO[47] | J5 | MA[5] | P11 | MD[12] |
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C16 | VSS | J6 | MA[4] | P12 | MD[31] |
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D1 | SDCLK[2] | J7 | VCC | P13 | nPOE/GPIO[48] |
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D2 | SDCLK[0] | J8 | VSS | P14 | nPCE[1]/GPIO[52] |
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D3 | RDnWR | J9 | VSS | P15 | VSSN |
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D4 | VCCN | J10 | VSSQ | P16 | nPSKTSEL/GPIO[54] |
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D5 | L_DD[10]/GPIO[68] | J11 | GPIO[5] | R1 | MA[18] |
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D6 | L_DD[5]/GPIO[63] | J12 | GPIO[4] | R2 | VSSN |
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D7 | L_DD[1]/GPIO[59] | J13 | nRESET | R3 | MA[20] |
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D8 | L_LCLK/GPIO[75] | J14 | VSSQ | R4 | VSSN |
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D9 | SSPTXD/GPIO[25] | J15 | PLL_VCC | R5 | MA[22] |
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D10 | nACRESET | J16 | PLL_VSS | R6 | VSSN |
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D11 | SCL | K1 | MA[8] | R7 | MD[25] |
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D12 | PWM[1]/GPIO[17] | K2 | MA[9] | R8 | VSSN |
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D13 | BTTXD/GPIO[43] | K3 | MD[19] | R9 | MD[10] |
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D14 | MMCMD | K4 | VCCN | R10 | VSSN |
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D15 | VCCQ | K5 | MA[10] | R11 | MD[30] |
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D16 | VSSQ | K6 | MA[11] | R12 | VSSN |
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E1 | nSDRAS | K7 | VSSQ | R13 | nCS[4]/GPIO[80] |
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E2 | VSSN | K8 | VCC | R14 | VSSN |
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E3 | SDCKE[1] | K9 | VSSQ | R15 | nPIOW/GPIO[51] |
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E4 | SDCKE[0] | K10 | VCC | R16 | nPCE[2]/GPIO[53] |
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E5 | L_DD[6]/GPIO[64] | K11 | nRESET_OUT | T1 | VSS |
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E6 | L_DD[4]/GPIO[62] | K12 | nBATT_FAULT | T2 | VCCN |
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E7 | L_DD[0]/GPIO[58] | K13 | nVDD_FAULT | T3 | MD[23] |
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E8 | L_FCLK/GPIO[74] | K14 | GPIO[3] | T4 | MA[21] |
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E9 | SSPSFRM/GPIO[24] | K15 | PXTAL | T5 | MA[24] |
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E10 | SDATA_IN0/GPIO[29] | K16 | PEXTAL | T6 | MD[3] |
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E11 | SYNC/GPIO[31] | L1 | MA[12] | T7 | MD[5] |
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PXA250 and PXA210 Applications Processors Design Guide |
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