Introduction

Table 1-3. Signal Pin Descriptions (Sheet 3 of 7)

Name

 

Type

Description

 

 

 

 

nPREG/

 

 

PCMCIA register select. Output signal that indicates the target address is attribute

 

ICOCZ

space, on a memory transaction. This signal has the same timing as address.

GPIO[55]

 

 

 

See Note [2]

 

 

 

 

 

 

 

LCD Controller Pins

 

 

 

 

 

 

L_DD(15:0)/

 

ICOCZ

LCD Controller display data

GPIO[73:58]

 

See Note [2]

 

 

 

 

 

 

L_FCLK/

 

ICOCZ

LCD Frame clock

GPIO[74]

 

See Note [2]

 

 

 

 

 

 

L_LCLK/

 

ICOCZ

LCD Line clock

GPIO[75]

 

See Note [2]

 

 

 

 

 

 

L_PCLK/

 

ICOCZ

LCD pixel clock

GPIO[76]

 

See Note [2]

 

 

 

 

 

 

L_BIAS/

 

ICOCZ

AC Bias Drive

GPIO[77]

 

See Note [2]

 

 

 

 

 

Full Function UART Pins

 

 

 

 

 

FFRXD/

 

ICOCZ

Full Function UART Receive pin

GPIO[34]

 

See Note [2]

 

 

 

 

 

 

FFTXD/

 

ICOCZ

Full Function UART Transmit pin

GPIO[39]

 

See Note [2]

 

 

 

 

 

 

FFCTS/

 

ICOCZ

Full Function UART Clear-to-Send pin

GPIO[35]

 

See Note [2]

 

 

 

 

 

 

FFDCD/

 

ICOCZ

Full Function UART Data-Carrier-Detect Pin

GPIO[36]

 

See Note [2]

 

 

 

 

 

 

FFDSR/

 

ICOCZ

Full Function UART Data-Set-Ready Pin:

GPIO[37]

 

See Note [2]

 

 

 

 

 

 

FFRI/

 

ICOCZ

Full Function UART Ring Indicator Pin

GPIO[38]

 

See Note [2]

 

 

 

 

 

 

FFDTR/

 

ICOCZ

Full Function UART Data-Terminal-Ready pin

GPIO[40]

 

See Note [2]

 

 

 

 

 

 

FFRTS/

 

ICOCZ

Full Function UART Ready-to-Send pin

GPIO[41]

 

See Note [2]

 

 

 

 

 

 

Bluetooth UART Pins

 

 

 

 

 

 

BTRXD/

 

ICOCZ

Bluetooth UART Receive pin

GPIO[42]

 

See Note [2]

 

 

 

 

 

 

BTTXD/

 

ICOCZ

Bluetooth UART Transmit pin

GPIO[43]

 

See Note [2]

 

 

 

 

 

 

BTCTS/

 

ICOCZ

Bluetooth UART Clear-to-Send pin

GPIO[44]

 

See Note [2]

 

 

 

 

 

 

BTRTS/

 

ICOCZ

Bluetooth UART Data-Terminal-Ready pin

GPIO[45]

 

See Note [2]

 

 

 

 

 

 

MMC Controller Pins

 

 

 

 

 

 

MMCMD

 

ICOCZ

Multimedia Card Command pin (I/O)

 

 

 

 

1-6

PXA250 and PXA210 Applications Processors Design Guide

Page 14
Image 14
Intel PXA250 and PXA210 manual Signal Pin Descriptions Sheet 3

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.