Power and Clocking
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 3 of 6)
Pin | Pin | Alt_fn | Alt_fn | Alt_fn | Alt_fn | Signal Description and | Power | |
Count | Comments | Supply | ||||||
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MMCMD | 1 |
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| MMC Command | VCCQ | |
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MMDAT | 1 |
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| MMC Data | VCCQ | |
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AC_RESET_n | 1 |
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| ac97 RESET | VCCQ | |
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UDC+ | 1 |
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| USB client high differential signal | VCCQ | |
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UDC- | 1 |
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| USB client low differential signal | VCCQ | |
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SCL | 1 |
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| I2C Clock | VCCQ | |
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SDA | 1 |
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| I2C Bidirectional Data | VCCQ | |
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nRESET | 1 |
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| Hardware reset | VCCQ | |
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nRESET_OUT | 1 |
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| Reset output | VCCQ | |
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BOOT_SEL[2:0] | 3 |
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| ROM Width Select (16/32) | VCCQ | |
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PWR_EN | 1 |
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| power enable | VCCQ | |
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nBATT_FAULT | 1 |
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| Battery Fault | VCCQ | |
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nVDD_FAULT | 1 |
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| VDD Fault | VCCQ | |
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nTRST | 1 |
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| JTAG Reset | VCCQ | |
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TDI | 1 |
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| JTAG Data In | VCCQ | |
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TDO | 1 |
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| JTAG Data Out | VCCQ | |
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TMS | 1 |
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| JTAG Mode Select | VCCQ | |
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TCK | 1 |
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| JTAG Clock | VCCQ | |
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TESTCLK | 1 |
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| TEST Clock | VCCQ | |
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TEST | 1 |
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| TEST mode | VCCQ | |
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GP0 | 1 |
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| Reserved for sleep wakeup | VCCQ | |
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GP1 | 1 | GP_RST |
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| Active low GP_reset | VCCQ | |
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GP2 | 1 |
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| General Purpose I/O pin | VCCQ | |
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GP3 | 1 |
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| General Purpose I/O pin | VCCQ | |
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GP4 | 1 |
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| General Purpose I/O pin | VCCQ | |
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GP5 | 1 |
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| General Purpose I/O pin | VCCQ | |
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GP6 | 1 |
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| MMCCLK |
| MMC Clock | VCCQ | |
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GP7 | 1 |
|
| 48 MHz |
| 48 mhz clock output | VCCQ | |
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GP8 | 1 |
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| MMCCS0 |
| MMC Chip Select 0 | VCCQ | |
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GP9 | 1 |
|
| MMCCS1 |
| MMC Chip Select 1 | VCCQ | |
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GP10 | 1 |
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| RTCCLK |
| real time clock (1Hz) | VCCQ | |
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PXA250 and PXA210 Applications Processors Design Guide |