Introduction

Table 1-3. Signal Pin Descriptions (Sheet 5 of 7)

Name

 

Type

Description

 

 

 

 

 

 

 

I2C Data signal (bidirectional).

SDA

 

ICOCZ

Bidirectional signal. When it is driving, it functions as an open collector device and

 

 

 

requires a pull up resistor. As an input, it expects standard CMOS levels.

 

 

 

 

PWM Pins

 

 

 

 

 

 

PWM[1:0]/

 

ICOCZ

Pulse Width Modulation channels 0 and 1 (outputs)

GPIO[17,16]

 

See Note [2]

 

 

 

 

 

 

Dedicated GPIO Pins

 

 

 

 

 

 

 

 

 

General Purpose I/O: These two pins are contained in both the PXA250 and PXA210

 

 

 

applications processors. They are preconfigured at a hard reset (nRESET) as wakeup

GPIO[1:0]

 

ICOCZ

sources for both rising and falling edge detects.

 

 

 

These GPIOs do not have alternate functions and are intended to be used as the main

 

 

 

external sleep wakeup stimulus.

 

 

 

 

 

 

 

General Purpose I/O

GPIO[14:2])

 

ICOCZ

See Note [1]

 

 

 

See Note [2]

 

 

 

 

GPIO[22:21]

 

ICOCZ

General Purpose I/O

 

Additional general purpose I/O pins.

 

 

 

 

 

 

 

Crystal Pins

 

 

 

 

 

 

PXTAL

 

IA

Input connection for 3.6864 Mhz crystal

 

 

 

 

PEXTAL

 

OA

Output connection for 3.6864 Mhz crystal

 

 

 

 

TXTAL

 

IA

Input connection for 32.768 khz crystal

 

 

 

 

TEXTAL

 

OA

Output connection for 32.768 khz crystal

 

 

 

 

48MHz/GP[7]

 

ICOCZ

48 MHz clock. (output) Peripheral clock output derived from the PLL.

 

 

 

 

RTCCLK/GP[10]

 

ICOCZ

Real time clock. (output) HZ output derived from the 32kHz or 3.6864MHz output.

 

 

 

 

3.6MHz/GP[11]

 

ICOCZ

3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.

 

 

 

 

32kHz/GP[12]

 

ICOCZ

32 kHz clock. (output) Output from the 32 kHz oscillator.

 

 

 

 

Miscellaneous Pins

 

 

 

 

 

 

 

 

 

Boot programming select pins. These pins are sampled to indicate the type of boot

 

 

 

device present per the following table;

 

 

 

BOOT_SEL[2:0] Description

BOOT_SEL

 

 

000Asynchronous 32-bit ROM

 

IC

001Asynchronous 16-bit ROM

[2:0]

 

 

 

100One 32-bit SMROM

 

 

 

 

 

 

101One 16 bit SMROM

 

 

 

110Two 16 bit SMROMs (32 bit bus)

 

 

 

111Reserved

 

 

 

 

 

 

 

Power Enable. Active high Output.

PWR_EN

 

OCZ

PWR_EN enables the external power supply. Negating it signals the power supply

 

that the system is going into sleep mode and that the VDD power supply should be

 

 

 

 

 

 

removed.

 

 

 

 

 

 

 

Battery Fault. Active low input.

nBATT_FAULT

 

IC

The assertion of nBATT_FAULT causes the applications processor to enter Sleep

 

Mode.The applications processor will not recognize a wakeup event while this signal

 

 

 

is asserted. Use nBATT_FAULT signal to flag a critical power failure, such as the main

 

 

 

battery being removed. Minimum assertion time for nBATT_FAULT is 1ms.

 

 

 

 

1-8

PXA250 and PXA210 Applications Processors Design Guide

Page 15 Page 17
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Intel PXA250 and PXA210 manual Signal Pin Descriptions Sheet 5
Page 15 Page 17

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.
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