Power and Clocking

Table 8-18. Synchronous Memory Interface AC Specifications (2.5 V)

Symbol

Description

MIN

MAX

Notes1

 

SDRAM / SMROM

 

 

 

 

 

 

 

 

tsynCLK

SDCLK period

 

 

 

 

 

 

 

 

tsynCMD

nSDCAS, nSDRAS, nWE, nSDCS assert time

 

 

 

 

 

 

 

 

tsynRCD

nSDRAS to nSDCAS assert time

 

 

 

 

 

 

 

 

tsynCAS

nSDCAS to nSDCAS assert time

 

 

 

 

 

 

 

 

tsynSDOS

MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE,

 

TBD

 

SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise

 

 

 

 

 

 

 

 

 

 

 

 

tsynSDOH

MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE,

 

 

 

SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise

 

 

 

 

 

 

 

 

 

 

 

 

tsynSDIS

MD(31:0) read data input setup time from SDCLK(2:0) rise

 

 

 

 

 

 

 

 

tsynDIH

MD(31:0) read data input hold time from SDCLK(2:0) rise

 

 

 

 

 

 

 

 

 

Fast Flash (Synchronous READS only)

 

 

 

 

 

 

 

 

tffCLK

SDCLK period

 

 

 

 

 

 

 

 

tffAS

MA(25:0) setup to nSDCAS (as nADV) asserted

 

 

 

 

 

 

 

 

tffCES

nCS setup to nSDCAS (as nADV) asserted

 

TBD

 

 

 

 

 

tffADV

nSDCAS (as nADV) pulse width

 

 

 

 

 

 

 

 

 

 

tffOS

nSDCAS (as nADV) deassertion to nOE assertion

 

 

 

 

 

 

 

 

tffCEH

nOE deassertion to nCS deassertion

 

 

 

 

 

 

 

 

NOTES:

1.These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK.

2.SDCLK for SDRAM and SMROM can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5 MHz at the fastest.

3.This number represents 1/2 SDCLK period.

4.SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz MEMCLK at its fastest.

8.7Example Form Factor Reference Design Power Delivery Example

8.7.1Power System

Features of the example form factor reference design power system (example in Figure 8-5, “Example Form Factor Reference Design Power System Design” on page 8-22) are:

•A standard-size cylindrical single-cell Li+ 3.6 V battery with a 1.8 Ahr capacity

•Battery temperature monitoring thermistor during charge cycles

•Battery voltage monitoring

•Charger supply voltage fault monitoring

•Low battery interrupt signal to the microprocessor.

8-20

PXA250 and PXA210 Applications Processors Design Guide

Page 87 Page 89
Page 88
Image 88
Intel PXA250 and PXA210 manual Example Form Factor Reference Design Power Delivery Example, Power System
Page 87 Page 89

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.
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