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Intel manual Introduction, PXA250 and PXA210 Applications Processors Design Guide

Models: PXA250 and PXA210

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Introduction

Table 1-5. PXA210 Applications Processor Pinout — Ballpad Number Order (Sheet 1 of 2)

Ball #	Signal	Ball #	Signal	Ball #	Signal

A1	DQM[1]	F1	VSSN	L1	VSSN

A2	L_DD[14]/GPIO[72]	F2	nSDCS[0]	L2	VCCN

A3	L_DD[10]/GPIO[68]	F3	nSDRAS	L3	MA[12]

A4	VSSQ	F4	nSDCS[1]	L4	MA[13]

A5	L_DD[6]/GPIO[64]	F5	VCC	L5	MA[11]

A6	L_DD[2]/GPIO[60]	F6	L_DD[8]/GPIO[66]	L6	VSSQ

A7	L_LCLK/GPIO[75]	F7	L_FCLK/GPIO[74]	L7	MD[2]

A8	SPPSCLK/GPIO[23]	F8	SSPRXD/GPIO[26]	L8	MD[6]

A9	SPPEXTCLK/GPIO[27]	F9	VCC	L9	VSSN

A10	nACRESET	F10	FFTXD/GPIO[39]	L10	MD[11]

A11	PWM[1]/GPIO[17]	F11	VCC	L11	BATT_VCC

A12	VSSQ	F12	VSSQ	L12	GPIO[54]

A13	FFRXD/GPIO[34]	F13	TESTCLK	L13	GPIO[55]

A14	BTCTS/GPIO[44]	F14	BOOT_SEL[0]	L14	GPIO[57]

A15	IRRXD/GPIO[46]	F15	TEST	L15	GPIO[0]

B1	RDY/GPIO[18]	G1	MA[0]	M1	MA[14]

B2	VSSN	G2	nOE	M2	MA[15]

B3	L_DD[13]/GPIO[71]	G3	nWE	M3	VCCN

B4	L_DD[9]/GPIO[67]	G4	VCCN	M4	MA[16]

B5	VSSQ	G5	VSSN	M5	VCCN

B6	L_DD[3]/GPIO[61]	G6	RDnWR	M6	VSSN

B7	L_PCLK/GPIO[76]	G7	VSS	M7	MD[3]

B8	VSSQ	G8	VSS	M8	MD[7]

B9	BITCLK/GPIO[28]	G9	VSS	M9	nCS[1]/GPIO[15]

B10	SDA	G10	BTRXD/GPIO[42]	M10	MD[10]

B11	VSSQ	G11	nTRST	M11	MD[13]

B12	USB_N	G12	TDI	M12	GPIO[48]

B13	BTRTS/GPIO[45]	G13	TCK	M13	GPIO[52]

B14	IRTXD/GPIO[47]	G14	TMS	M14	VSSN

B15	MMDAT	G15	TDO	M15	GPIO[56]

C1	SDCKE[1]	H1	VCCN	N1	VSSN

C2	SDCKE[0]	H2	VSSN	N2	MA[18]

C3	VCCN	H3	MA[2]	N3	VSS1

C4	L_DD[12]/GPIO[70]	H4	MA[1]	N4	MA[22]

C5	VCCQ	H5	VCC	N5	MA[24]

C6	L_DD[4]/GPIO[62]	H6	VSSQ	N6	VCCN

C7	L_BIAS/GPIO[77]	H7	VSS	N7	VCC

1-16	PXA250 and PXA210 Applications Processors Design Guide

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Intel manual Introduction, PXA250 and PXA210 Applications Processors Design Guide

Contents

Design Guide Intel PXA250 and PXA210 Applications ProcessorsFebruary Order NumberPXA250 and PXA210 Applications Processors Design Guide Contents ContentsUSB Interface PXA250 and PXA210 Applications Processors Design GuideContents MultiMediaCard MMCAC97 PXA250 and PXA210 Applications Processors Design GuideContents Example Form Factor Reference Design Schematic DiagramsPXA250 and PXA210 Applications Processors Design Guide Figures TablesContents PXA250 and PXA210 Applications Processors Design GuideContents PXA250 and PXA210 Applications Processors Design GuideContents PXA250 and PXA210 Applications Processors Design GuideIntroduction 1.1 Functional OverviewRevision History Table 1-2. Related Documentation1.2 Package Information 1.2.1 Package IntroductionFigure 1-1. Applications Processor Block Diagram OS TimerIntroduction PXA250 and PXA210 Applications Processors Design Guide1.2.2 Signal Pin Descriptions Table 1-3. Signal Pin Descriptions Sheet 1 ofIntroduction PXA250 and PXA210 Applications Processors Design GuideTable 1-3. Signal Pin Descriptions Sheet 2 of IntroductionPXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 3 of IntroductionPXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 4 of IntroductionPXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 5 of BOOTSEL20 DescriptionIntroduction PXA250 and PXA210 Applications Processors Design GuideTable 1-3. Signal Pin Descriptions Sheet 6 of IntroductionPXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 7 of IntroductionPXA250 and PXA210 Applications Processors Design Guide Introduction Figure 1-2. PXA250 Applications Processor1-11 PXA250 and PXA210 Applications Processors Design GuideIntroduction PXA250 and PXA210 Applications Processors Design GuideIntroduction 1-13PXA250 and PXA210 Applications Processors Design Guide Introduction PXA250 and PXA210 Applications Processors Design GuideIntroduction Figure 1-3. PXA210 Applications Processor1-15 PXA250 and PXA210 Applications Processors Design GuideIntroduction PXA250 and PXA210 Applications Processors Design GuideIntroduction 1-17PXA250 and PXA210 Applications Processors Design Guide Introduction PXA250 and PXA210 Applications Processors Design GuideSystem Memory Interface 2.1 OverviewPXA250 and PXA210 Applications Processors Design Guide Figure 2-1. General Memory Interface Configuration System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide Card Memory Interface2.3 SDRAM memory wiring diagram 2.2 SDRAM InterfaceSystem Memory Interface Table 2-1. Memory Address MapSystem Memory Interface Figure 2-2. SDRAM Memory System ExamplePXA250 and PXA210 Applications Processors Design Guide 2.4 SDRAM Support System Memory InterfaceTable 2-2. SDRAM Memory Types Supported by the Applications Processor PXA250 and PXA210 Applications Processors Design Guide2.5 SDRAM Address Mapping System Memory InterfaceTable 2-3. Normal Mode Memory Address Mapping PXA250 and PXA210 Applications Processors Design Guide2.6 Static Memory 2.6.1 OverviewSystem Memory Interface PXA250 and PXA210 Applications Processors Design Guide2.6.2 Boot Time Defaults Table 2-5. Valid Booting Configurations Based on Package TypeTable 2-6. BOOTSEL Definitions Sheet 1 of System Memory Interface2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options 2.6.4 Variable Latency I/O Interface OverviewTable 2-6. BOOTSEL Definitions Sheet 2 of System Memory InterfaceSystem Memory Interface PXA250 and PXA210 Applications Processors Design Guidememlk nCS02.6.5 External Logic for PCMCIA Implementation System Memory Interface2-11 System Memory Interface PXA250 and PXA210 Applications Processors Design GuidePXA250 Applications Processor SocketSystem Memory Interface 2-13PXA250 Socket2.6.6 DMA / Companion Chip Interface System Memory InterfaceConnect a companion chip to the applications processor via Alternate Bus Master Mode Variable Latency I/O Flow through DMAPXA250 MemoryController PXA250PXA250 System Memory InterfaceFigure 2-7. Variable Latency I/O EXTERNAL SYSTEM2.7 System Memory Layout Guidelines 2.7.1 System Memory Topologies Min and Max Simulated LoadingCS, CKE, DQM CLK, MA CS, CKE, DQM CLK, MA2.7.2 System Memory Recommended Trace Lengths Table 2-10. Minimum and Maximum Trace Lengths for the SDRAM SignalsSystem Memory Interface Figure 2-11. MD maximum loading topologyLCD Display Controller 3.1 LCD Display Overview3.2 Passive DSTN Displays Table 3-1. LCD Controller Data Pin Utilization Sheet 1 of3.2.1 Typical Connections for Passive Panel Displays Table 3-2. Passive Display Pins Required3.2.1.1 Passive Monochrome Single Panel Displays LCD Display Controller3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data 3.2.1.3 Passive Monochrome Dual Panel DisplaysLCD Display Controller PXA250 and PXA210 Applications Processor Design Guide3.2.1.4 Passive Color Single Panel Displays 3.2.1.5 Passive Color Dual Panel DisplaysLCD Display Controller Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection3.3 Active TFT Displays LCD Display ControllerFigure 3-5. Passive Color Dual Panel Displays Typical Connection PXA250 and PXA210 Applications Processor Design Guide3.3.1 Typical connections for Active Panel Displays Table 3-3. Active Display Pins RequiredLCD Display Controller PXA250 and PXA210 Applications Processor Design Guide3.4 PXA250 Pinout LCD Display ControllerFigure 3-6. Active Color Display Typical Connection Table 3-4. PXA250 LCD Controller Ball Positions Sheet 1 of3.5.3 Signal Routing and Buffering 3.5 Additional Design Considerations3.5.1 Contrast Voltage 3.5.2 Backlight Inverter3.5.4 Panel Connector LCD Display ControllerPXA250 and PXA210 Applications Processor Design Guide LCD Display Controller PXA250 and PXA210 Applications Processor Design Guide4.1 Self Powered Device 4.1.1 Operation if GPIOn and GPIOx are Different PinsUSB Interface Figure 4-1. Self Powered Device4.2 Bus Powered Device 4.1.2 Operation if GPIOn and GPIOx are the Same PinUSB Interface PXA250 and PXA210 Applications Processors Design Guide5.1 Schematics 5.1.1 Signal DescriptionMultiMediaCard MMC Table 5-1. MMC Signal Description5.1.2 How to Wire Table 5-2. SDCard Socket SignalsMultiMediaCard MMC Table 5-3. MMC Controller Supported Sockets and DevicesFigure 5-1. Applications Processor MMC and SDCard Signal Connections MultiMediaCard MMC5.1.2.1 SDCard Socket 5.1.2.2 MMC SocketMultiMediaCard MMC PXA250 and PXA210 Applications Processors Design Guide5.1.3 Simplified Schematic MultiMediaCard MMC5.2 Utilized Features 5.1.4 Pull-up and Pull-downMultiMediaCard MMC Table 5-4. SDCard Pull-up and Pull-down Resistors6.1 Schematics AC97Figure 6-1. AC97 connection PXA250 and PXA210 Applications Processors Design Guide6.2 Layout AC97PXA250 and PXA210 Applications Processors Design Guide 7.1 Schematics 7.1.1 Signal DescriptionTable 7-1. I2C Signal Description PXA250 and PXA210 Applications Processors Design Guide7.1.2 Digital-to-Analog Converter DAC 7.1.3 Other Uses of I2CFigure 7-1. Linear Technology DAC with I2C Interface PXA250 and PXA210 Applications Processors Design Guide7.1.4 Pull-Ups and Pull-Downs Figure 7-2. Using an Analog Switch to Allow a Second CF CardFigure 7-3. I2C Pull-Ups and Pull-Downs PXA250 and PXA210 Applications Processors Design Guide7.2 Utilized Features PXA250 and PXA210 Applications Processors Design GuidePower and Clocking 8.1 Operating ConditionsPXA250 and PXA210 Applications Processors Design Guide 8.2 Electrical Specifications 8.3 Power Consumption SpecificationsPower and Clocking Table 8-2. Absolute Maximum RatingsPower and Clocking Table 8-3. Power Consumption Specifications Sheet 1 of8.4 Oscillator Electrical Specifications 8.4.1 32.768 kHz Oscillator SpecificationsPower and Clocking Table 8-3. Power Consumption Specifications Sheet 2 of8.4.2 3.6864 MHz Oscillator Specifications Power and ClockingTable 8-4. 32.768 kHz Oscillator Specifications Sheet 2 of Table 8-5. 3.6864 MHz Oscillator Specifications8.5 Reset and Power AC Timing Specifications 8.5.1 Power Supply ConnectivityPower and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 1 ofPower and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 2 ofPXA250 and PXA210 Applications Processors Design Guide Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 3 ofPXA250 and PXA210 Applications Processors Design Guide Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 4 ofPXA250 and PXA210 Applications Processors Design Guide Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 5 ofPXA250 and PXA210 Applications Processors Design Guide 8.5.2 Power On Timing Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 6 of 8-118.5.3 Hardware Reset Timing Power and ClockingFigure 8-1. Power-On Reset Timing JTAG PINS8.5.4 Watchdog Reset Timing 8.5.5 GPIO Reset TimingPower and Clocking Figure 8-2. Hardware Reset Timing8.5.6 Sleep Mode Timing Power and ClockingTable 8-9. GPIO Reset Timing Specifications GPx PWREN VCC nVDDFAULT nRESETOUT8.6 Memory Bus and PCMCIA AC Specifications Power and ClockingTable 8-10. Sleep Mode Timing Specifications Sheet 2 of 8-15Power and Clocking Table 8-12. Variable Latency I/O Interface AC SpecificationsPXA250 and PXA210 Applications Processors Design Guide Power and Clocking Table 8-14. Synchronous Memory Interface AC Specifications 3.38-17 PXA250 and PXA210 Applications Processors Design GuidePower and Clocking PXA250 and PXA210 Applications Processors Design GuidePower and Clocking Table 8-16. Variable Latency I/O Interface AC Specifications 2.58-19 PXA250 and PXA210 Applications Processors Design Guide8.7 Example Form Factor Reference Design Power Delivery Example 8.7.1 Power SystemPower and Clocking Table 8-18. Synchronous Memory Interface AC Specifications 2.58.7.1.1 Power System Configuration Power and Clocking8-21 8.7.2 CORE Power 8.7.3 PLL PowerPower and Clocking Figure 8-5. Example Form Factor Reference Design Power System Design8.7.4 I/O 3.3 V Power 8.7.5 Peripheral 5.5 V PowerPower and Clocking 8-23Power and Clocking PXA250 and PXA210 Applications Processors Design Guide9.2 Schematics JTAG/Debug Port9.1 Description Figure 9-1. JTAG/Debug Port Wiring Diagram9.3 Layout JTAG/Debug PortPXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications Processor MigrationPXA250 and PXA210 Applications Processors Design Guide A.1 SA-1110 Hardware Migration Issues A.1.2 Signal ChangesA.1.1 Hardware Compatibility Table A-1. PXA250 Boot Select Options Sheet 1 ofTable A-1. PXA250 Boot Select Options Sheet 2 of Figure A-1. Write Enable Control PinsSA-1110 PXA250A.1.3 Power Delivery A.1.4 PackageA.1.5 Clocks SA-1110/Applications Processor MigrationA.2 SA-1110 to PXA250 Software Migration Issues A.1.6 UCB1300SA-1110/Applications Processor Migration PXA250 and PXA210 Applications Processors Design GuideA.2.4 Configuration registers A.2.1 Software CompatibilityA.2.2 Address space A.2.3 Page Table ChangesA.3 Using New PXA250 Features A.2.5 DMASA-1110/Applications Processor Migration PXA250 and PXA210 Applications Processors Design GuideA.3.4 Other features A.3.1 Intel XScale MicroarchitectureA.3.2 Debugging A.3.3 Cache AttributesA.3.5 Conclusion SA-1110/Applications Processor MigrationPXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications Processor Migration A-10PXA250 and PXA210 Applications Processors Design Guide Schematic Diagrams B.2 Schematic DiagramsExample Form Factor Reference Design B.1 NotesPage Pg.2 Intel PXA250 ProcessorAddress and Data Buses RESET Pg.3Intel PXA250 Processor Capacitors for CoreSYSTEM CONFIGURATION REGISTER SDRAMSDRAM Bank Addressing Flash Memory Resistor StrataFlashSynchronous StrataFlashBuffer Board ControlRegister CPLDTransceivers 74LVCH16245A74LVCH16245A 74LVCH16245AAudio CODEC Audio AmpUCB1400 Modem / AudioIrDA Transceiver Headset JackMicrophone SpeakerMomentary Switches Three Position SwitchBase Station Connector Compact Flash Type II SocketConnector JTAG ICE ConnectorSD Socket RadioBattery Connector Battery Charger5.5 Volt Supply Processor Core Voltage SupplyLCD CPLD Note Onboard Back Light InverterLCD Power Sharp LCD ConnectorConnector Toshiba LCD ConnectorExpansion ExpansionHeader HeaderRevision Tracking Changes Example Form Factor Reference Design Schematic Diagrams B-18PXA250 and PXA210 Applications Processors Design Guide Schematic Diagram C.1 Schematic DiagramBBPXA2xx Development Baseboard PXA250 and PXA210 Applications Processors Design GuideTable of Contents BBPXA2xxPage Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page BBPXA2xx Development Baseboard Schematic Diagram C-40PXA250 and PXA210 Applications Processors Design Guide PXA250 Processor Card Schematic DiagramD.1 Schematic Diagram PXA250 and PXA210 Applications Processors Design GuideTABLE OF CONTENTS DCPXA250 Processor Card 32-bit version7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER Page Page Page Page Page Page Page Page Page Page PXA210 Processor Card Schematic E.1 Schematic DiagramDiagram The DCPXA210 processor card schematic is on the following pagesDCPXA210 Processor Card 16-bit version TABLE OF CONTENTSCONNECTOR MEMORY and I/O SIGNALS PAGEPage Page Page Page Page Page Page Page Page Page Page Page PXA210 Processor Card Schematic Diagram PXA250 and PXA210 Applications Processors Design Guide