Introduction
s
Figure 1-1. Applications Processor Block Diagram
RTC |
OS Timer |
PWM(2) |
Int. |
Controller |
PurposeI/O | Clocks & | PeripheralBus | ControllerDMA | Bridgeand |
AC97 | ||||
| Power Man. |
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| I2S |
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| I2C |
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General | UART1 |
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| UART2 |
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| Slow IrDA |
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| Fast IrDA |
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SSP |
USB |
Client |
MMC |
Color or
Grayscale
LCD
Controller
System Bus
Megacell
Core
3.6864 32.768
MHz KHz
Osc Osc
Memory
Controller
Variable |
|
Latency I/O | ASIC |
Control |
|
PCMCIA | XCVR | Socket 0 |
& CF | Socket 1 | |
Control |
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Dynamic |
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| SDRAM/ |
| SMROM | |||
Memory |
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| 4 banks | |||
Control |
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Static |
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| ROM/ |
| Flash/ | |||
Memory |
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| SRAM | |
Control |
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| 4 banks | |||
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The PXA250 applications processor package is: 256 pin, 17x17 mBGA –
PXA210 applications processor package is: 225 pin, 13x13 MMAP –
Section 1.2.1, “Package Introduction” contains a breakdown of the features supported by the two different packages.
1.2Package Information
This section describes the package types, pinouts, and signal descriptions.
1.2.1Package Introduction
Package features of the PXA250 applications processor are:
•Core frequencies supported - 100 MHz - 400 MHz
PXA250 and PXA210 Applications Processors Design Guide |