Intel PXA250 and PXA210 manual System Memory Interface, memlk, nCS0, MA10

System Memory Interface

data has been latched, the address may change on the next rising edge of MEMCLK or any cycles thereafter. The nOE or nPWE signal de-asserts one MEMCLK after data is latched. Before a subsequent data beat, nOE or nPWE remains deasserted for RDN+1 memory cycles. The chip select and byte selects, DQM[3:0], remain asserted for one memory cycle after the burst’s final nOE or nPWE deassertion. Refer to Figure 2-3for 32-Bit Variable Latency I/O read timing and Figure 2-8for Variable Latency I/O Interface AC Specifications

Figure 2-3. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)

0ns

100ns

200ns

300ns

memlk
nCS[0]
	tAS
MA[25:2]	0
MA[1:0]
	tASRW0

tAH

tCES

nOE nPWE RDnWR

RDY MD[31:0] DQM[3:0] nCS[1]

1	2	3
	"00"
tASWN
		tCEH
RDN+1		RRR+1
	RDF+1+Waits

"0000"

A8867-01

Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 1 of 2)

				MEMCKLK				Units
Symbol	Description
		99.5	118.0		132.7	147.5	165.9	Notes
Variable Latency IO Interface (VLIO) (Asynchronous)
tvlioAS	MA(25:0) setup to nCS asserted	10	8.5		7.5	6.8	6	ns, 1
tvlioASRW	MA(25:0) setup to nOE or nPWE	10	8.5		7.5	6.8	6	ns, 1
	asserted
tvlioAH	MA(25:0) hold after nOE or nPWE de-	10	8.5		7.5	6.8	6	ns, 1
	asserted
tvlioCES	nCS setup to nOE or nPWE asserted	20	17		15	13.6	12	ns, 2
tvlioCEH	nCS hold after nOE or nPWE de-	10	8.5		7.5	6.8	6	ns, 1
	asserted

2-10 PXA250 and PXA210 Applications Processors Design Guide