System Memory Interface

data has been latched, the address may change on the next rising edge of MEMCLK or any cycles thereafter. The nOE or nPWE signal de-asserts one MEMCLK after data is latched. Before a subsequent data beat, nOE or nPWE remains deasserted for RDN+1 memory cycles. The chip select and byte selects, DQM[3:0], remain asserted for one memory cycle after the burst’s final nOE or nPWE deassertion. Refer to Figure 2-3for 32-Bit Variable Latency I/O read timing and Figure 2-8for Variable Latency I/O Interface AC Specifications

Figure 2-3. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)

0ns

100ns

200ns

300ns

memlk

 

nCS[0]

 

 

tAS

MA[25:2]

0

MA[1:0]

 

 

tASRW0

tAH

tCES

nOE nPWE RDnWR

RDY MD[31:0] DQM[3:0] nCS[1]

1

2

3

 

"00"

 

tASWN

 

 

 

 

tCEH

RDN+1

 

RRR+1

 

RDF+1+Waits

 

 

"0000"

A8867-01

Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 1 of 2)

 

 

 

 

MEMCKLK

 

 

Units

Symbol

Description

 

 

 

 

 

 

 

99.5

118.0

 

132.7

 

147.5

165.9

Notes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Variable Latency IO Interface (VLIO) (Asynchronous)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioAS

MA(25:0) setup to nCS asserted

10

8.5

 

7.5

 

6.8

6

ns, 1

 

 

 

 

 

 

 

 

 

 

tvlioASRW

MA(25:0) setup to nOE or nPWE

10

8.5

 

7.5

 

6.8

6

ns, 1

asserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioAH

MA(25:0) hold after nOE or nPWE de-

10

8.5

 

7.5

 

6.8

6

ns, 1

asserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tvlioCES

nCS setup to nOE or nPWE asserted

20

17

 

15

 

13.6

12

ns, 2

 

 

 

 

 

 

 

 

 

 

tvlioCEH

nCS hold after nOE or nPWE de-

10

8.5

 

7.5

 

6.8

6

ns, 1

asserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-10

PXA250 and PXA210 Applications Processors Design Guide

Page 35 Page 37
Page 36
Image 36
Intel PXA250 and PXA210 manual Variable Latency I/O Interface AC Specifications Sheet 1, Memcklk
Page 35 Page 37

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.
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