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PXA250 and PXA210 manual BBPXA2xx Development Baseboard Schematic Diagram, C-40
Models:
PXA250 and PXA210
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Specification
1. Applications Processor Block Diagram
1. General Memory Interface Configuration
How to Wire
A.1 SA-1110 Hardware Migration Issues
1. Power-On Reset Timing
Boot Time Defaults
Signal Pin Descriptions
Battery Connector
Self Powered Device
Page 162
Image 162
BBPXA2xx Development Baseboard Schematic Diagram
C-40
PXA250 and PXA210 Applications Processors Design Guide
Page 161
Page 163
Page 162
Image 162
Page 161
Page 163
Contents
February
Design Guide
Intel PXA250 and PXA210 Applications Processors
Order Number
PXA250 and PXA210 Applications Processors Design Guide
USB Interface
Contents
Contents
PXA250 and PXA210 Applications Processors Design Guide
AC97
Contents
MultiMediaCard MMC
PXA250 and PXA210 Applications Processors Design Guide
Contents
Example Form Factor Reference Design Schematic Diagrams
PXA250 and PXA210 Applications Processors Design Guide
Contents
Figures
Tables
PXA250 and PXA210 Applications Processors Design Guide
Contents
PXA250 and PXA210 Applications Processors Design Guide
Contents
PXA250 and PXA210 Applications Processors Design Guide
Revision History
Introduction
1.1 Functional Overview
Table 1-2. Related Documentation
Figure 1-1. Applications Processor Block Diagram
1.2 Package Information
1.2.1 Package Introduction
OS Timer
Introduction
PXA250 and PXA210 Applications Processors Design Guide
Introduction
1.2.2 Signal Pin Descriptions
Table 1-3. Signal Pin Descriptions Sheet 1 of
PXA250 and PXA210 Applications Processors Design Guide
Table 1-3. Signal Pin Descriptions Sheet 2 of
Introduction
PXA250 and PXA210 Applications Processors Design Guide
Table 1-3. Signal Pin Descriptions Sheet 3 of
Introduction
PXA250 and PXA210 Applications Processors Design Guide
Table 1-3. Signal Pin Descriptions Sheet 4 of
Introduction
PXA250 and PXA210 Applications Processors Design Guide
Introduction
Table 1-3. Signal Pin Descriptions Sheet 5 of
BOOTSEL20 Description
PXA250 and PXA210 Applications Processors Design Guide
Table 1-3. Signal Pin Descriptions Sheet 6 of
Introduction
PXA250 and PXA210 Applications Processors Design Guide
Table 1-3. Signal Pin Descriptions Sheet 7 of
Introduction
PXA250 and PXA210 Applications Processors Design Guide
1-11
Introduction
Figure 1-2. PXA250 Applications Processor
PXA250 and PXA210 Applications Processors Design Guide
Introduction
PXA250 and PXA210 Applications Processors Design Guide
Introduction
1-13
PXA250 and PXA210 Applications Processors Design Guide
Introduction
PXA250 and PXA210 Applications Processors Design Guide
1-15
Introduction
Figure 1-3. PXA210 Applications Processor
PXA250 and PXA210 Applications Processors Design Guide
Introduction
PXA250 and PXA210 Applications Processors Design Guide
Introduction
1-17
PXA250 and PXA210 Applications Processors Design Guide
Introduction
PXA250 and PXA210 Applications Processors Design Guide
System Memory Interface
2.1 Overview
PXA250 and PXA210 Applications Processors Design Guide
PXA250 and PXA210 Applications Processors Design Guide
Figure 2-1. General Memory Interface Configuration
System Memory Interface
Card Memory Interface
System Memory Interface
2.3 SDRAM memory wiring diagram
2.2 SDRAM Interface
Table 2-1. Memory Address Map
System Memory Interface
Figure 2-2. SDRAM Memory System Example
PXA250 and PXA210 Applications Processors Design Guide
Table 2-2. SDRAM Memory Types Supported by the Applications Processor
2.4 SDRAM Support
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
Table 2-3. Normal Mode Memory Address Mapping
2.5 SDRAM Address Mapping
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
System Memory Interface
2.6 Static Memory
2.6.1 Overview
PXA250 and PXA210 Applications Processors Design Guide
Table 2-6. BOOTSEL Definitions Sheet 1 of
2.6.2 Boot Time Defaults
Table 2-5. Valid Booting Configurations Based on Package Type
System Memory Interface
Table 2-6. BOOTSEL Definitions Sheet 2 of
2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options
2.6.4 Variable Latency I/O Interface Overview
System Memory Interface
memlk
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
nCS0
2.6.5 External Logic for PCMCIA Implementation
System Memory Interface
2-11
PXA250 Applications Processor
System Memory Interface
PXA250 and PXA210 Applications Processors Design Guide
Socket
PXA250
System Memory Interface
2-13
Socket
Connect a companion chip to the applications processor via
2.6.6 DMA / Companion Chip Interface
System Memory Interface
Alternate Bus Master Mode Variable Latency I/O Flow through DMA
Controller
PXA250
Memory
PXA250
Figure 2-7. Variable Latency I/O
PXA250
System Memory Interface
EXTERNAL SYSTEM
CS, CKE, DQM CLK, MA
2.7 System Memory Layout Guidelines
2.7.1 System Memory Topologies Min and Max Simulated Loading
CS, CKE, DQM CLK, MA
System Memory Interface
2.7.2 System Memory Recommended Trace Lengths
Table 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals
Figure 2-11. MD maximum loading topology
3.2 Passive DSTN Displays
LCD Display Controller
3.1 LCD Display Overview
Table 3-1. LCD Controller Data Pin Utilization Sheet 1 of
3.2.1.1 Passive Monochrome Single Panel Displays
3.2.1 Typical Connections for Passive Panel Displays
Table 3-2. Passive Display Pins Required
LCD Display Controller
LCD Display Controller
3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data
3.2.1.3 Passive Monochrome Dual Panel Displays
PXA250 and PXA210 Applications Processor Design Guide
LCD Display Controller
3.2.1.4 Passive Color Single Panel Displays
3.2.1.5 Passive Color Dual Panel Displays
Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection
Figure 3-5. Passive Color Dual Panel Displays Typical Connection
3.3 Active TFT Displays
LCD Display Controller
PXA250 and PXA210 Applications Processor Design Guide
LCD Display Controller
3.3.1 Typical connections for Active Panel Displays
Table 3-3. Active Display Pins Required
PXA250 and PXA210 Applications Processor Design Guide
Figure 3-6. Active Color Display Typical Connection
3.4 PXA250 Pinout
LCD Display Controller
Table 3-4. PXA250 LCD Controller Ball Positions Sheet 1 of
3.5.1 Contrast Voltage
3.5.3 Signal Routing and Buffering
3.5 Additional Design Considerations
3.5.2 Backlight Inverter
3.5.4 Panel Connector
LCD Display Controller
PXA250 and PXA210 Applications Processor Design Guide
LCD Display Controller
PXA250 and PXA210 Applications Processor Design Guide
USB Interface
4.1 Self Powered Device
4.1.1 Operation if GPIOn and GPIOx are Different Pins
Figure 4-1. Self Powered Device
USB Interface
4.2 Bus Powered Device
4.1.2 Operation if GPIOn and GPIOx are the Same Pin
PXA250 and PXA210 Applications Processors Design Guide
MultiMediaCard MMC
5.1 Schematics
5.1.1 Signal Description
Table 5-1. MMC Signal Description
MultiMediaCard MMC
5.1.2 How to Wire
Table 5-2. SDCard Socket Signals
Table 5-3. MMC Controller Supported Sockets and Devices
Figure 5-1. Applications Processor MMC and SDCard Signal Connections
MultiMediaCard MMC
MultiMediaCard MMC
5.1.2.1 SDCard Socket
5.1.2.2 MMC Socket
PXA250 and PXA210 Applications Processors Design Guide
5.1.3 Simplified Schematic
MultiMediaCard MMC
MultiMediaCard MMC
5.2 Utilized Features
5.1.4 Pull-up and Pull-down
Table 5-4. SDCard Pull-up and Pull-down Resistors
Figure 6-1. AC97 connection
6.1 Schematics
AC97
PXA250 and PXA210 Applications Processors Design Guide
6.2 Layout
AC97
PXA250 and PXA210 Applications Processors Design Guide
Table 7-1. I2C Signal Description
7.1 Schematics
7.1.1 Signal Description
PXA250 and PXA210 Applications Processors Design Guide
Figure 7-1. Linear Technology DAC with I2C Interface
7.1.2 Digital-to-Analog Converter DAC
7.1.3 Other Uses of I2C
PXA250 and PXA210 Applications Processors Design Guide
Figure 7-3. I2C Pull-Ups and Pull-Downs
7.1.4 Pull-Ups and Pull-Downs
Figure 7-2. Using an Analog Switch to Allow a Second CF Card
PXA250 and PXA210 Applications Processors Design Guide
7.2 Utilized Features
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
8.1 Operating Conditions
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
8.2 Electrical Specifications
8.3 Power Consumption Specifications
Table 8-2. Absolute Maximum Ratings
Power and Clocking
Table 8-3. Power Consumption Specifications Sheet 1 of
Power and Clocking
8.4 Oscillator Electrical Specifications
8.4.1 32.768 kHz Oscillator Specifications
Table 8-3. Power Consumption Specifications Sheet 2 of
Table 8-4. 32.768 kHz Oscillator Specifications Sheet 2 of
8.4.2 3.6864 MHz Oscillator Specifications
Power and Clocking
Table 8-5. 3.6864 MHz Oscillator Specifications
Power and Clocking
8.5 Reset and Power AC Timing Specifications
8.5.1 Power Supply Connectivity
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 1 of
Power and Clocking
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 2 of
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 3 of
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 4 of
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 5 of
PXA250 and PXA210 Applications Processors Design Guide
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 6 of
8.5.2 Power On Timing
Power and Clocking
8-11
Figure 8-1. Power-On Reset Timing
8.5.3 Hardware Reset Timing
Power and Clocking
JTAG PINS
Power and Clocking
8.5.4 Watchdog Reset Timing
8.5.5 GPIO Reset Timing
Figure 8-2. Hardware Reset Timing
Table 8-9. GPIO Reset Timing Specifications
8.5.6 Sleep Mode Timing
Power and Clocking
GPx PWREN VCC nVDDFAULT nRESETOUT
Table 8-10. Sleep Mode Timing Specifications Sheet 2 of
8.6 Memory Bus and PCMCIA AC Specifications
Power and Clocking
8-15
Power and Clocking
Table 8-12. Variable Latency I/O Interface AC Specifications
PXA250 and PXA210 Applications Processors Design Guide
8-17
Power and Clocking
Table 8-14. Synchronous Memory Interface AC Specifications 3.3
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
8-19
Power and Clocking
Table 8-16. Variable Latency I/O Interface AC Specifications 2.5
PXA250 and PXA210 Applications Processors Design Guide
Power and Clocking
8.7 Example Form Factor Reference Design Power Delivery Example
8.7.1 Power System
Table 8-18. Synchronous Memory Interface AC Specifications 2.5
8.7.1.1 Power System Configuration
Power and Clocking
8-21
Power and Clocking
8.7.2 CORE Power
8.7.3 PLL Power
Figure 8-5. Example Form Factor Reference Design Power System Design
Power and Clocking
8.7.4 I/O 3.3 V Power
8.7.5 Peripheral 5.5 V Power
8-23
Power and Clocking
PXA250 and PXA210 Applications Processors Design Guide
9.1 Description
9.2 Schematics
JTAG/Debug Port
Figure 9-1. JTAG/Debug Port Wiring Diagram
9.3 Layout
JTAG/Debug Port
PXA250 and PXA210 Applications Processors Design Guide
SA-1110/Applications Processor
Migration
PXA250 and PXA210 Applications Processors Design Guide
A.1.1 Hardware Compatibility
A.1 SA-1110 Hardware Migration Issues
A.1.2 Signal Changes
Table A-1. PXA250 Boot Select Options Sheet 1 of
SA-1110
Table A-1. PXA250 Boot Select Options Sheet 2 of
Figure A-1. Write Enable Control Pins
PXA250
A.1.5 Clocks
A.1.3 Power Delivery
A.1.4 Package
SA-1110/Applications Processor Migration
SA-1110/Applications Processor Migration
A.2 SA-1110 to PXA250 Software Migration Issues
A.1.6 UCB1300
PXA250 and PXA210 Applications Processors Design Guide
A.2.2 Address space
A.2.4 Configuration registers
A.2.1 Software Compatibility
A.2.3 Page Table Changes
SA-1110/Applications Processor Migration
A.3 Using New PXA250 Features
A.2.5 DMA
PXA250 and PXA210 Applications Processors Design Guide
A.3.2 Debugging
A.3.4 Other features
A.3.1 Intel XScale Microarchitecture
A.3.3 Cache Attributes
A.3.5 Conclusion
SA-1110/Applications Processor Migration
PXA250 and PXA210 Applications Processors Design Guide
SA-1110/Applications Processor Migration
A-10
PXA250 and PXA210 Applications Processors Design Guide
Example Form Factor Reference Design
Schematic Diagrams
B.2 Schematic Diagrams
B.1 Notes
Page
Pg.2
Intel PXA250 Processor
Address and Data Buses
Intel PXA250 Processor
RESET
Pg.3
Capacitors for Core
SYSTEM CONFIGURATION REGISTER
SDRAM
SDRAM Bank Addressing
Synchronous
Flash Memory
Resistor StrataFlash
StrataFlash
Register
Buffer
Board Control
CPLD
74LVCH16245A
Transceivers
74LVCH16245A
74LVCH16245A
UCB1400
Audio CODEC
Audio Amp
Modem / Audio
Microphone
IrDA Transceiver
Headset Jack
Speaker
Base Station Connector
Momentary Switches
Three Position Switch
Compact Flash Type II Socket
SD Socket
Connector
JTAG ICE Connector
Radio
5.5 Volt Supply
Battery Connector
Battery Charger
Processor Core Voltage Supply
board Back
LCD CPLD
Note On
Light Inverter
Connector
LCD Power
Sharp LCD Connector
Toshiba LCD Connector
Header
Expansion
Expansion
Header
Revision Tracking Changes
Example Form Factor Reference Design Schematic Diagrams
B-18
PXA250 and PXA210 Applications Processors Design Guide
BBPXA2xx Development Baseboard
Schematic Diagram
C.1 Schematic Diagram
PXA250 and PXA210 Applications Processors Design Guide
Table of Contents
BBPXA2xx
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BBPXA2xx Development Baseboard Schematic Diagram
C-40
PXA250 and PXA210 Applications Processors Design Guide
D.1 Schematic Diagram
PXA250 Processor Card Schematic
Diagram
PXA250 and PXA210 Applications Processors Design Guide
TABLE OF CONTENTS
DCPXA250 Processor Card 32-bit version
7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER
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Diagram
PXA210 Processor Card Schematic
E.1 Schematic Diagram
The DCPXA210 processor card schematic is on the following pages
CONNECTOR MEMORY and I/O SIGNALS
DCPXA210 Processor Card 16-bit version
TABLE OF CONTENTS
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PXA210 Processor Card Schematic Diagram
PXA250 and PXA210 Applications Processors Design Guide
