System Memory Interface

Memory types are programmable through the memory interface configuration registers.

Six chip selects control the static memory interface, nCS<5:0>. All are configurable for nonburst ROM or Flash memory, burst ROM or Flash, SRAM, or SRAM-like variable latency I/O devices. The variable latency I/O interface differs from SRAM in that it allows the data ready input signal (RDY) to insert a variable number of memory-cycle-wait states. The data bus width for each chip select region may be programmed to be 16-bit or 32-bit. nCS<3:0> are also configurable for Synchronous Static Memory.

For SRAM and variable latency I/O implementations, DQM<3:0> signals are used for the write byte enables, where DQM<3> corresponds to the MSB. The applications processor supplies 26- bits of byte address for access of up to 64 Mbytes per chip select. However, when the address is sent out on the MA pins, MA reflects the actual address, not the byte address. The lower one or two internal address bits are truncated appropriately.

2.6.2Boot Time Defaults

Booting configuration is device specific. For example, you cannot use a 32-bit memory booting configuration with a PXA210 applications processor. Table 2-5shows valid booting configurations based on processor type, while Table 2-6shows boot selection definitions. See Section 7.10.2, “Boot-Time Configurations” in the Intel® PXA250 and PXA210 Applications Processors Developer’s Manual for more detailed descriptions of these Boot Time Configurations.

Table 2-5. Valid Booting Configurations Based on Package Type

Processor Type

Valid Booting Configurations

 

 

0 (PXA210

001

 

 

applications

101

processor)

 

111

 

 

 

 

000

 

 

 

001

1 (PXA250

 

100

applications

 

101

processor)

 

 

 

110

 

 

 

111

 

 

Table 2-6. BOOT_SEL Definitions (Sheet 1 of 2)

 

BOOT_SEL

 

 

 

 

 

Boot From . . .

2

1

0

 

 

 

 

 

0

0

0

Asynchronous 32-bit ROM

 

 

 

 

0

0

1

Asynchronous 16-bit ROM

 

 

 

 

1

0

0

1 32-bit Synchronous Mask ROM (64 Mbits)

 

2 16-bit Synchronous Mask ROMs = 32-bits (32 Mbits each)

2-8

PXA250 and PXA210 Applications Processors Design Guide

Page 33 Page 35
Page 34
Image 34
Intel PXA250 and PXA210 manual Boot Time Defaults, Valid Booting Configurations Based on Package Type, Boot From
Page 33 Page 35

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.
Top Page Image Contents