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Intel PXA250 and PXA210 manual Reset and Power AC Timing Specifications, Power Supply Connectivity

Models: PXA250 and PXA210

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Power and Clocking

•Drive the PEXTAL pin with a digital signal that has a low level near 0 V and a high level near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 1 V per 100 ns. The maximum current drawn by the external clock source when the clock is at its maximum positive voltage should be about 1 mA.

•Float the PXTAL pin or drive it complementary to the PEXTAL pin, using the same voltage level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility will be introduced in the system, and it is therefore not recommended.

8.5Reset and Power AC Timing Specifications

The applications processor asserts the nRESET_OUT pin in one of several modes:

•Power On

•Hardware Reset

•Watchdog Reset

•GPIO Reset

•Sleep Mode

The following sections give the timing and other specifications for the entry and exit of these modes.

8.5.1Power Supply Connectivity

The PXA250 applications processor requires two or three externally-supplied voltage levels. VCCQ requires high voltage, VCCN requires high or medium voltage, and VCC and PLL_VCC require low voltage. PLL_VCC must be separated from other low voltage supplies. Depending on the availability of independent regulator outputs and the desired memory voltage, VCCQ may have to be separated from VCCN. VCCN does not have to be separated at the board level.

Note: Shaded sections are not supported for the PXA210 applications processor.

Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 1 of 6)

	Pin	Pin	Alt_fn	Alt_fn	Alt_fn	Alt_fn	Signal Description and	Power
	Pin	Count	1-(in)	2-(in)	1-(out)	2-(out)	Comments	Supply
		Count	1-(in)	2-(in)	1-(out)	2-(out)	Comments	Supply

	MA(25:0)	26					Main Memory Address Bus	VCCN

	MD(31:16)	16					Main Memory Data Bus (high)	VCCN

	MD(15:0)	16					Main Memory Data Bus (low)	VCCN

	nOE	1					Main Memory Bus Output Enable	VCCN

	nWE	1					Main Memory Bus Write Enable	VCCN

	nSDRAS	1					Main Memory Bus RAS	VCCN

	nSDCAS	1					Main Memory Bus CAS	VCCN

	DQM(3:2)	2					Main Memory Bus SDRAM byte	VCCN
	DQM(3:2)	2					selects	VCCN
							selects

8-6	PXA250 and PXA210 Applications Processors Design Guide

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Intel PXA250 and PXA210 manual Reset and Power AC Timing Specifications, Power Supply Connectivity, Power and Clocking

Contents

February Design GuideIntel PXA250 and PXA210 Applications Processors Order NumberPXA250 and PXA210 Applications Processors Design Guide USB Interface ContentsContents PXA250 and PXA210 Applications Processors Design GuideAC97 ContentsMultiMediaCard MMC PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide ContentsExample Form Factor Reference Design Schematic Diagrams Contents FiguresTables PXA250 and PXA210 Applications Processors Design GuideContents PXA250 and PXA210 Applications Processors Design GuideContents PXA250 and PXA210 Applications Processors Design GuideRevision History Introduction1.1 Functional Overview Table 1-2. Related DocumentationFigure 1-1. Applications Processor Block Diagram 1.2 Package Information1.2.1 Package Introduction OS TimerIntroduction PXA250 and PXA210 Applications Processors Design GuideIntroduction 1.2.2 Signal Pin DescriptionsTable 1-3. Signal Pin Descriptions Sheet 1 of PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 2 ofIntroduction PXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 3 ofIntroduction PXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 4 ofIntroduction Introduction Table 1-3. Signal Pin Descriptions Sheet 5 ofBOOTSEL20 Description PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 6 ofIntroduction PXA250 and PXA210 Applications Processors Design Guide Table 1-3. Signal Pin Descriptions Sheet 7 ofIntroduction 1-11 IntroductionFigure 1-2. PXA250 Applications Processor PXA250 and PXA210 Applications Processors Design GuideIntroduction PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Introduction1-13 Introduction PXA250 and PXA210 Applications Processors Design Guide1-15 IntroductionFigure 1-3. PXA210 Applications Processor PXA250 and PXA210 Applications Processors Design GuideIntroduction PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Introduction1-17 Introduction PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide System Memory Interface2.1 Overview PXA250 and PXA210 Applications Processors Design Guide Figure 2-1. General Memory Interface ConfigurationSystem Memory Interface Card Memory InterfaceSystem Memory Interface 2.3 SDRAM memory wiring diagram2.2 SDRAM Interface Table 2-1. Memory Address MapPXA250 and PXA210 Applications Processors Design Guide System Memory InterfaceFigure 2-2. SDRAM Memory System Example Table 2-2. SDRAM Memory Types Supported by the Applications Processor 2.4 SDRAM SupportSystem Memory Interface PXA250 and PXA210 Applications Processors Design GuideTable 2-3. Normal Mode Memory Address Mapping 2.5 SDRAM Address MappingSystem Memory Interface PXA250 and PXA210 Applications Processors Design GuideSystem Memory Interface 2.6 Static Memory2.6.1 Overview PXA250 and PXA210 Applications Processors Design GuideTable 2-6. BOOTSEL Definitions Sheet 1 of 2.6.2 Boot Time DefaultsTable 2-5. Valid Booting Configurations Based on Package Type System Memory InterfaceTable 2-6. BOOTSEL Definitions Sheet 2 of 2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options2.6.4 Variable Latency I/O Interface Overview System Memory Interfacememlk System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide nCS02-11 2.6.5 External Logic for PCMCIA ImplementationSystem Memory Interface PXA250 Applications Processor System Memory InterfacePXA250 and PXA210 Applications Processors Design Guide SocketPXA250 System Memory Interface2-13 SocketConnect a companion chip to the applications processor via 2.6.6 DMA / Companion Chip InterfaceSystem Memory Interface Alternate Bus Master Mode Variable Latency I/O Flow through DMAController PXA250Memory PXA250Figure 2-7. Variable Latency I/O PXA250System Memory Interface EXTERNAL SYSTEMCS, CKE, DQM CLK, MA 2.7 System Memory Layout Guidelines2.7.1 System Memory Topologies Min and Max Simulated Loading CS, CKE, DQM CLK, MASystem Memory Interface 2.7.2 System Memory Recommended Trace LengthsTable 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals Figure 2-11. MD maximum loading topology3.2 Passive DSTN Displays LCD Display Controller3.1 LCD Display Overview Table 3-1. LCD Controller Data Pin Utilization Sheet 1 of3.2.1.1 Passive Monochrome Single Panel Displays 3.2.1 Typical Connections for Passive Panel DisplaysTable 3-2. Passive Display Pins Required LCD Display ControllerLCD Display Controller 3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data3.2.1.3 Passive Monochrome Dual Panel Displays PXA250 and PXA210 Applications Processor Design GuideLCD Display Controller 3.2.1.4 Passive Color Single Panel Displays3.2.1.5 Passive Color Dual Panel Displays Figure 3-3. Passive Monochrome Dual Panel Displays Typical ConnectionFigure 3-5. Passive Color Dual Panel Displays Typical Connection 3.3 Active TFT DisplaysLCD Display Controller PXA250 and PXA210 Applications Processor Design GuideLCD Display Controller 3.3.1 Typical connections for Active Panel DisplaysTable 3-3. Active Display Pins Required PXA250 and PXA210 Applications Processor Design GuideFigure 3-6. Active Color Display Typical Connection 3.4 PXA250 PinoutLCD Display Controller Table 3-4. PXA250 LCD Controller Ball Positions Sheet 1 of3.5.1 Contrast Voltage 3.5.3 Signal Routing and Buffering3.5 Additional Design Considerations 3.5.2 Backlight InverterPXA250 and PXA210 Applications Processor Design Guide 3.5.4 Panel ConnectorLCD Display Controller LCD Display Controller PXA250 and PXA210 Applications Processor Design GuideUSB Interface 4.1 Self Powered Device4.1.1 Operation if GPIOn and GPIOx are Different Pins Figure 4-1. Self Powered DeviceUSB Interface 4.2 Bus Powered Device4.1.2 Operation if GPIOn and GPIOx are the Same Pin PXA250 and PXA210 Applications Processors Design GuideMultiMediaCard MMC 5.1 Schematics5.1.1 Signal Description Table 5-1. MMC Signal DescriptionMultiMediaCard MMC 5.1.2 How to WireTable 5-2. SDCard Socket Signals Table 5-3. MMC Controller Supported Sockets and DevicesFigure 5-1. Applications Processor MMC and SDCard Signal Connections MultiMediaCard MMCMultiMediaCard MMC 5.1.2.1 SDCard Socket5.1.2.2 MMC Socket PXA250 and PXA210 Applications Processors Design Guide5.1.3 Simplified Schematic MultiMediaCard MMCMultiMediaCard MMC 5.2 Utilized Features5.1.4 Pull-up and Pull-down Table 5-4. SDCard Pull-up and Pull-down ResistorsFigure 6-1. AC97 connection 6.1 SchematicsAC97 PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide 6.2 LayoutAC97 Table 7-1. I2C Signal Description 7.1 Schematics7.1.1 Signal Description PXA250 and PXA210 Applications Processors Design GuideFigure 7-1. Linear Technology DAC with I2C Interface 7.1.2 Digital-to-Analog Converter DAC7.1.3 Other Uses of I2C PXA250 and PXA210 Applications Processors Design GuideFigure 7-3. I2C Pull-Ups and Pull-Downs 7.1.4 Pull-Ups and Pull-DownsFigure 7-2. Using an Analog Switch to Allow a Second CF Card PXA250 and PXA210 Applications Processors Design Guide7.2 Utilized Features PXA250 and PXA210 Applications Processors Design GuidePXA250 and PXA210 Applications Processors Design Guide Power and Clocking8.1 Operating Conditions Power and Clocking 8.2 Electrical Specifications8.3 Power Consumption Specifications Table 8-2. Absolute Maximum RatingsPower and Clocking Table 8-3. Power Consumption Specifications Sheet 1 ofPower and Clocking 8.4 Oscillator Electrical Specifications8.4.1 32.768 kHz Oscillator Specifications Table 8-3. Power Consumption Specifications Sheet 2 ofTable 8-4. 32.768 kHz Oscillator Specifications Sheet 2 of 8.4.2 3.6864 MHz Oscillator SpecificationsPower and Clocking Table 8-5. 3.6864 MHz Oscillator SpecificationsPower and Clocking 8.5 Reset and Power AC Timing Specifications8.5.1 Power Supply Connectivity Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 1 ofPXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 2 of PXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 3 of PXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 4 of PXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 5 of Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ Sheet 6 of 8.5.2 Power On TimingPower and Clocking 8-11Figure 8-1. Power-On Reset Timing 8.5.3 Hardware Reset TimingPower and Clocking JTAG PINSPower and Clocking 8.5.4 Watchdog Reset Timing8.5.5 GPIO Reset Timing Figure 8-2. Hardware Reset TimingTable 8-9. GPIO Reset Timing Specifications 8.5.6 Sleep Mode TimingPower and Clocking GPx PWREN VCC nVDDFAULT nRESETOUTTable 8-10. Sleep Mode Timing Specifications Sheet 2 of 8.6 Memory Bus and PCMCIA AC SpecificationsPower and Clocking 8-15PXA250 and PXA210 Applications Processors Design Guide Power and ClockingTable 8-12. Variable Latency I/O Interface AC Specifications 8-17 Power and ClockingTable 8-14. Synchronous Memory Interface AC Specifications 3.3 PXA250 and PXA210 Applications Processors Design GuidePower and Clocking PXA250 and PXA210 Applications Processors Design Guide8-19 Power and ClockingTable 8-16. Variable Latency I/O Interface AC Specifications 2.5 PXA250 and PXA210 Applications Processors Design GuidePower and Clocking 8.7 Example Form Factor Reference Design Power Delivery Example8.7.1 Power System Table 8-18. Synchronous Memory Interface AC Specifications 2.58-21 8.7.1.1 Power System ConfigurationPower and Clocking Power and Clocking 8.7.2 CORE Power8.7.3 PLL Power Figure 8-5. Example Form Factor Reference Design Power System DesignPower and Clocking 8.7.4 I/O 3.3 V Power8.7.5 Peripheral 5.5 V Power 8-23Power and Clocking PXA250 and PXA210 Applications Processors Design Guide9.1 Description 9.2 SchematicsJTAG/Debug Port Figure 9-1. JTAG/Debug Port Wiring DiagramPXA250 and PXA210 Applications Processors Design Guide 9.3 LayoutJTAG/Debug Port PXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications ProcessorMigration A.1.1 Hardware Compatibility A.1 SA-1110 Hardware Migration IssuesA.1.2 Signal Changes Table A-1. PXA250 Boot Select Options Sheet 1 ofSA-1110 Table A-1. PXA250 Boot Select Options Sheet 2 ofFigure A-1. Write Enable Control Pins PXA250A.1.5 Clocks A.1.3 Power DeliveryA.1.4 Package SA-1110/Applications Processor MigrationSA-1110/Applications Processor Migration A.2 SA-1110 to PXA250 Software Migration IssuesA.1.6 UCB1300 PXA250 and PXA210 Applications Processors Design GuideA.2.2 Address space A.2.4 Configuration registersA.2.1 Software Compatibility A.2.3 Page Table ChangesSA-1110/Applications Processor Migration A.3 Using New PXA250 FeaturesA.2.5 DMA PXA250 and PXA210 Applications Processors Design GuideA.3.2 Debugging A.3.4 Other featuresA.3.1 Intel XScale Microarchitecture A.3.3 Cache AttributesPXA250 and PXA210 Applications Processors Design Guide A.3.5 ConclusionSA-1110/Applications Processor Migration PXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications Processor MigrationA-10 Example Form Factor Reference Design Schematic DiagramsB.2 Schematic Diagrams B.1 NotesPage Address and Data Buses Pg.2Intel PXA250 Processor Intel PXA250 Processor RESETPg.3 Capacitors for CoreSDRAM Bank Addressing SYSTEM CONFIGURATION REGISTERSDRAM Synchronous Flash MemoryResistor StrataFlash StrataFlashRegister BufferBoard Control CPLD74LVCH16245A Transceivers74LVCH16245A 74LVCH16245AUCB1400 Audio CODECAudio Amp Modem / AudioMicrophone IrDA TransceiverHeadset Jack SpeakerBase Station Connector Momentary SwitchesThree Position Switch Compact Flash Type II SocketSD Socket ConnectorJTAG ICE Connector Radio5.5 Volt Supply Battery ConnectorBattery Charger Processor Core Voltage Supplyboard Back LCD CPLDNote On Light InverterConnector LCD PowerSharp LCD Connector Toshiba LCD ConnectorHeader ExpansionExpansion HeaderRevision Tracking Changes PXA250 and PXA210 Applications Processors Design Guide Example Form Factor Reference Design Schematic DiagramsB-18 BBPXA2xx Development Baseboard Schematic DiagramC.1 Schematic Diagram PXA250 and PXA210 Applications Processors Design GuideTable of Contents BBPXA2xxPage Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page PXA250 and PXA210 Applications Processors Design Guide BBPXA2xx Development Baseboard Schematic DiagramC-40 D.1 Schematic Diagram PXA250 Processor Card SchematicDiagram PXA250 and PXA210 Applications Processors Design Guide7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER TABLE OF CONTENTSDCPXA250 Processor Card 32-bit version Page Page Page Page Page Page Page Page Page Page Diagram PXA210 Processor Card SchematicE.1 Schematic Diagram The DCPXA210 processor card schematic is on the following pagesCONNECTOR MEMORY and I/O SIGNALS DCPXA210 Processor Card 16-bit versionTABLE OF CONTENTS PAGEPage Page Page Page Page Page Page Page Page Page Page Page PXA210 Processor Card Schematic Diagram PXA250 and PXA210 Applications Processors Design Guide