Introduction
•I2C Controller pins
•PWM pins
•2 dedicated GPIOs pins
•Integrated JTAG support
1.2.2Signal Pin Descriptions
Table
Table 1-3. Signal Pin Descriptions (Sheet 1 of 7)
Name | Type | Description | |
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Memory Controller Pins |
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MA[25:0] | OCZ | Memory address bus. This bus signals the address requested for memory accesses. | |
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MD[15:0] | ICOCZ | Memory data bus. D[15:0] are used for | |
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| Memory data bus. D[31:16]: These signals are the upper memory data bus address | |
MD[31:16] | ICOCZ | bits. | |
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| See Note [1] | |
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nOE | OCZ | Memory output enable. Connect this signal to the output enables of memory devices | |
to control their data bus drivers. | |||
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nWE | OCZ | Memory write enable. Connect this signal to the write enables of memory devices. | |
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nSDCS[3:0] | OCZ | SDRAM CS for banks 0 through 3. Connect these signals to the chip select (CS) pins | |
for SDRAM. nSDCS0 is a | |||
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DQM[3:0] | OCZ | SDRAM DQM for data bytes 0 through 3. Connect these signals to the data output | |
mask enables (DQM) for SDRAM. | |||
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nSDRAS | OCZ | SDRAM RAS. Connect this signal to the row address strobe (RAS) pins for all banks | |
of SDRAM. | |||
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nSDCAS | OCZ | SDRAM CAS. Connect this signal to the column address strobe (CAS) pins for all | |
banks of SDRAM. | |||
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| SDRAM and/or Synchronous Static | |
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| enable clock enable. | |
SDCKE[0] | OC | ConnectSDCKE[0] to the CKE pins of SMROM and | |
Flash. | |||
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| The memory controller provides control register bits for deassertion of each SDCKE | |
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| pin. | |
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| SDRAM device clock enable. | |
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| Connect SDCKE[1] to the clock enable pins of SDRAM. It is | |
SDCKE[1] | OC | during sleep. SDCKE[1] is always deasserted upon reset. | |
The memory controller provides control register bits for deassertion of each SDCKE | |||
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| pin. | |
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| See Note [1] | |
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| Use these clocks to clock synchronous memory devices: | |
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| SDCLK0 - connected to either SMROM or synchronous Flash devices | |
SDCLK[2:0] | OCZ | SDCLK1 - connected to SDRAM banks 0/1 | |
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| SDCLK2 - connected to SDRAM banks 2/3 | |
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| See Note [1] | |
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PXA250 and PXA210 Applications Processors Design Guide |