Intel PXA250 and PXA210 manual Power and Clocking, 4. Sleep Mode Timing

Power and Clocking

Table 8-9. GPIO Reset Timing Specifications

Symbol	Description	Min	Typical	Max
tA_GP[1]	Minimum assert time of GP[1]1 in 3.6864 MHz input clock cycles	4 cycles	—	—
tDGP_OUT_A	Delay between GP[1] Asserted and nRESET_OUT Asserted in	6 cycles	—	8 cycles
	3.6864 MHz input clock cycles
tDGP_OUT	Delay between nRESET_OUT asserted and nRESET_OUT	5 ∝s	—	28 ∝s
	deasserted, Run or Turbo Mode2
tDGP_OUT_F	Delay between nRESET_OUT asserted and nRESET_OUT	5 ∝s	—	380 ∝s
	3
	deasserted, during Frequency Change Sequence

NOTES:

1.GP[1] is not recognized as a reset source again until configured to do so in software. Software should check the state of GP[1] before configuring it as a Reset to ensure no spurious reset is generated.

2.Time is 512*N Processor Clock Cycles plus as many as 4 cycles of the 3.6864 MHz input clock.

3.Time during the Frequency Change Sequence depends on the state of the PLL Lock Detector at the assertion of GPIO Reset. The Lock Detector has a maximum time of 350 us plus synchronization.

8.5.6Sleep Mode Timing

Sleep Mode is internally asserted, and asserts the nRESET_OUT and PWR_EN signals. The sequence indicated in Figure 8-4 “Sleep Mode Timing” and detailed in Table 8-10, “Sleep Mode Timing Specifications” on page 8-14are the required timing parameters for Sleep Mode.

Figure 8-4. Sleep Mode Timing

tA_GP[x]

GP[x]

PWR_EN

VCC

nVDD_FAULT

nRESET_OUT

tD_PWR_F tD_PWR_R

tDSM_VCC

tD_FAULT

tDSM_OUT

Note: nBATT_FAULT must be high or PXA250 will not exit Sleep Mode

Table 8-10. Sleep Mode Timing Specifications (Sheet 1 of 2)

Symbol	Description	Min	Typical	Max
tA_GP[x}	Assert Time of GPIO Wake up Source (x=[15:0])	91.6 ∝s	—	—
tD_PWR_F	Delay from nRESET_OUT asserted to PWR_EN deasserted	61 ∝s	—	91.6 ∝s
tD_PWR_R	Delay between GP[x] asserted to PWR_EN asserted	30.5 ∝s	—	122.1 ∝s
tDSM_VCC	Delay between PWR_EN asserted and VCC stable	—	—	10 ms

8-14 PXA250 and PXA210 Applications Processors Design Guide