Introduction

Table 1-3. Signal Pin Descriptions (Sheet 6 of 7)

 

 

 

Name

Type

Description

 

 

 

 

 

VDD Fault. Active low input.

nVDD_FAULT

IC

nVDD_FAULT causes the applications processor to enter Sleep Mode. nVDD_FAULT

is ignored after a wakeup event until the power supply timer completes (approximately

 

 

10 ms). use the nVDD_FAULT signal to flag a low battery. Minimum assertion time for

 

 

nVDD_FAULT is 1 ms.

 

 

 

 

 

Hard reset. Active low input.

 

 

nRESET is a level sensitive input which starts the processor from a known address. A

nRESET

IC

LOW level causes the current instruction to terminate abnormally, and all on-chip state

to be reset. When nRESET is driven HIGH, the processor re-starts from address 0.

 

 

nRESET must remain LOW until the power supply is stable and the internal 3.6864

 

 

MHz oscillator has come up to speed. While nRESET is LOW the processor performs

 

 

idle cycles.

 

 

 

 

 

Reset Out. Active low output.

nRESET_OUT

OC

This signal is asserted when nRESET is asserted and de-asserts after nRESET is

negated but before the first instruction fetch. nRESET_OUT is also asserted for “soft”

 

 

 

 

reset events (sleep, watchdog reset, GPIO reset)

 

 

 

JTAG Pins

 

 

 

 

 

 

 

JTAG Test Interface Reset. Resets the JTAG/Debug port. If JTAG/Debug is used,

 

 

drive nTRST from low to high either before or at the same time as nRESET. If JTAG is

nTRST

IC

not used, nTRST must be either tied to nRESET or tied low. Intel recommends that a

 

 

JTAG/Debug port be added to all systems for debug and download. See Chapter 9 for

 

 

details.

 

 

 

TDI

IC

JTAG test interface data input. Note this pin has an internal pullup resistor.

 

 

 

TDO

OCZ

JTAG test interface data output. Note this pin does NOT have an internal pullup

resistor.

 

 

 

 

 

TMS

IC

JTAG test interface mode select. Note this pin has an internal pullup resistor.

 

 

 

 

 

JTAG test interface reference Clock. TCK is the reference clock for all transfers on the

TCK

IC

JTAG test interface.

 

 

NOTE: This pin needs an external pulldown resistor.

 

 

 

TEST

IC

Test Mode. You should ground this pin. This pin is for manufacturing purposes only.

 

 

 

TESTCLK

IC

Test Clock. Use this pin for test purposes only. An end user should ground this pin.

 

 

 

Power and Ground Pins

 

 

 

 

VCC

SUP

Positive supply for the internal logic. Connect this supply to the low voltage (.85 -

1.65v) supply on the PCB.

 

 

 

 

 

VSS

SUP

Ground supply for the internal logic. Connect these pins to the common ground plane

on the PCB.

 

 

 

 

 

PLL_VCC

SUP

Positive supply for PLLs and oscillators must be shorted to VCC.

 

 

 

PLL_VSS

SUP

Ground supply for the PLL. Must be connected to common ground plane on the PCB.

 

 

 

VCCQ

SUP

Positive supply for all CMOS I/O except memory bus and PCMCIA pins. Connect

these pins to the common 3.3v supply on the PCB.

 

 

 

 

 

VSSQ

SUP

Ground supply for all CMOS I/O except memory bus and PCMCIA pins. Connect

these pins to the common ground plane on the PCB.

 

 

 

 

 

VCCN

SUP

Positive supply for memory bus and PCMCIA pins. Connect these pins to the common

3.3 V or 2.5 V supply on the PCB.

 

 

 

 

 

PXA250 and PXA210 Applications Processors Design Guide

1-9

Page 16 Page 18
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Image 17
Intel PXA250 and PXA210 manual Signal Pin Descriptions Sheet 6
Page 16 Page 18

PXA250 and PXA210 specifications

The Intel PXA250 and PXA210 processors, part of the Intel XScale architecture, were introduced in the early 2000s, targeting mobile and embedded applications. They are known for their low power consumption, high performance, and advanced multimedia capabilities, making them suitable for a wide range of devices, including PDAs, smartphones, and other portable computing devices.

The PXA250, which operates at clock speeds ranging from 400 MHz to 624 MHz, features a superscalar architecture that allows it to issue multiple instructions per clock cycle. This enhances the overall performance for demanding applications while maintaining low power usage. It supports a variety of peripheral interfaces, including USB, Ethernet, and various memory types, which contributes to its versatility in different product designs.

One of the key technologies in the PXA250 is the integrated Intel Smart Repeat Technology, which optimizes data processing, thereby reducing the amount of power consumed during operation. This feature is particularly important for battery-powered devices, as it extends the overall battery life, allowing for longer usage times in mobile environments. Additionally, the PXA250 includes a dedicated graphics acceleration unit, which enables enhanced graphics and multimedia performance suited to modern applications at the time.

In contrast, the PXA210 is a more entry-level processor, aimed at cost-sensitive applications. Operating at lower clock speeds, typically around 200 MHz to 400 MHz, it forgoes some of the advanced performance features of the PXA250 while still offering a good balance of performance and power efficiency. The PXA210 is less complex, making it suitable for simpler devices that do not require the extensive capabilities of the PXA250.

Both processors utilize the Intel XScale architecture, which is based on the ARM instruction set. They are built on a 0.13-micron process technology, enabling higher density and lower power consumption compared to their predecessors. With integrated memory controllers and bus interfaces, they facilitate efficient data handling and connectivity options.

In summary, both the Intel PXA250 and PXA210 processors played a crucial role in the evolution of mobile computing by providing powerful processing capabilities with energy efficiency. Their features and technologies enabled device manufacturers to create innovative products that catered to the growing demand for portable devices during that era.
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