Configuration Options

Table A-8. System Clock Options

Primary System Clock Reference

Possible Settings (LTU, Models 8747, 8777): DSX-1 Port 1, DSX-1 Port 2,

DSX-1 Port 3, DSX-1 Port 4, DSX-1 Port 5, DSX-1 Port 6, DSX-1 Port 7, DSX-1 Port 8, Internal

Default Setting: Internal

Possible Settings (LTU, Model 8779): G.703 Port 1, G.703 Port 2, G.703 Port 3,

G.703 Port 4, G.703 Port 5, G.703 Port 6, G.703 Port 7, G.703 Port 8, Internal Default Setting: Internal

Possible Settings (NTU): DSL Port 1, DSL Port 2, DSL Port 3,

DSL Port 4, DSL Port 5, DSL Port 6, DSL Port 7, DSL Port 8, Internal Default Setting: Internal

Determines the source of system timing. Select the most accurate clock available.

DSX-1or G.703 Port n – Timing is derived from the specified port. To be a valid clock source, the port must be enabled and must derive its timing from the DSX-1 or G.703 network.

DSL Port n – Timing is derived from the specified port. The port must be enabled and in a cross-connection.

Internal – Timing is derived from the internal oscillator, which provides a Stratum 4 reference.

Secondary System Clock Reference

Possible Settings (LTU, Models 8747, 8777): DSX-1 Port 1, DSX-1 Port 2,

DSX-1 Port 3, DSX-1 Port 4, DSX-1 Port 5, DSX-1 Port 6, DSX-1 Port 7, DSX-1 Port 8, Internal

Default Setting: Internal

Possible Settings (LTU, Model 8779): G.703 Port 1, G.703 Port 2, G.703 Port 3,

G.703 Port 4, G.703 Port 5, G.703 Port 6, G.703 Port 7, G.703 Port 8, Internal Default Setting: Internal

Possible Settings (NTU): DSL Port 1, DSL Port 2, DSL Port 3,

DSL Port 4, DSL Port 5, DSL Port 6, DSL Port 7, DSL Port 8, Internal Default Setting: Internal

Determines the source of system timing if the primary system clock source fails. If the secondary clock source fails, the unit switches to secondary holdover mode.

DSX-1or G.703 Port n – Timing is derived from the specified port. To be a valid clock source, the port must be enabled and must derive its timing from the DSX-1 or G.703 network.

DSL Port n – Timing is derived from the specified port. The port must be enabled and in a cross-connection.

Internal – Timing is derived from the internal oscillator, which provides a Stratum 4 reference.

A-16

April 2000

8700-A2-GB20-00

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Image 100
Paradyne 8747, 8777, 8779 Table A-8. System Clock Options, Primary System Clock Reference, Secondary System Clock Reference