2 Troubleshooting Procedures | 2.4 System Board Troubleshooting |
Table
D port | Contents | |
Status | ||
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| Clears software rest bit. | |
| Permits A20 line. | |
| Initializes special register and Intel chipset. | |
F000h | Initializes PIT CH0 only (for HOLD_ON). | |
| Initializes flag of factor rewriting of BIOS. | |
| Checks CHECK SUM. | |
| Transition to protect mode. | |
| Calculates the checksum of Boot block? HLT at checksum error | |
| Calculates the checksum of block other than Boot block. | |
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F001h | Checks rewriting EC/KBC? Goes to BIOS rewriting process at request for | |
| rewriting. | |
| Executes KBC initializing sequence. | |
| Transmits KBC enable command. | |
| Checks F12 key. | |
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F002h | Checks for request of BIOS rewriting? Checksum error of blocks other than | |
| BootBlock, at the request of F12 rewriting request. | |
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F003h | Transfers the process to the System BIOS IRT side. | |
| BIOS rewriting process | |
| Initializes peculiar HW to the model. | |
| Initializes GPIO I/O space. | |
| Permits BIOS writing. | |
| Controls serial interrupts. | |
| Releases the | |
| Permits the SMBus I/O space. | |
| Permits the access to SMBus. | |
| Configuration of DRAM | |
| Permits cache (only L1 Cache). | |
| Memory clear | |
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PORTEGE A200 Maintenance Manual (960 |