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Xilinx ML561 manual Table A-2FPGA #2 Pinout Signal Name

Models: ML561

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Appendix A: FPGA Pinouts

Table A-2:FPGA #2 Pinout (Continued)

Signal Name		Pin		Signal Name	Pin

	DDR2 DIMM Wide Interface (cont.)

DDR2_DIMM_DQ_BY15_B5		AD5		DDR2_DIMM_DQ_CB8_15_B4	N7

DDR2_DIMM_DQ_BY15_B6		AD4		DDR2_DIMM_DQ_CB8_15_B5	N8

DDR2_DIMM_DQ_BY15_B7		Y8		DDR2_DIMM_DQ_CB8_15_B6	M5

DDR2_DIMM_DQ_BY8_B0		G13		DDR2_DIMM_DQ_CB8_15_B7	M6

DDR2_DIMM_DQ_BY8_B1		F13		DDR2_DIMM_DQS_BY10_L_N	J9

DDR2_DIMM_DQ_BY8_B2		N9		DDR2_DIMM_DQS_BY10_L_P	J10

DDR2_DIMM_DQ_BY8_B3		N10		DDR2_DIMM_DQS_BY11_L_N	J7

DDR2_DIMM_DQ_BY8_B4		E13		DDR2_DIMM_DQS_BY11_L_P	H7

DDR2_DIMM_DQ_BY8_B5		E12		DDR2_DIMM_DQS_BY12_L_N	U7

DDR2_DIMM_DQ_BY8_B6		L9		DDR2_DIMM_DQS_BY12_L_P	T8

DDR2_DIMM_DQ_BY8_B7		M10		DDR2_DIMM_DQS_BY13_L_N	AF6

DDR2_DIMM_DQ_BY9_B0		A13		DDR2_DIMM_DQS_BY13_L_P	AE7

DDR2_DIMM_DQ_BY9_B1		H9		DDR2_DIMM_DQS_BY14_L_N	V7

DDR2_DIMM_DQ_BY9_B2		H10		DDR2_DIMM_DQS_BY14_L_P	W7

DDR2_DIMM_DQ_BY9_B3		C12		DDR2_DIMM_DQS_BY15_L_N	AF5

DDR2_DIMM_DQ_BY9_B4		D12		DDR2_DIMM_DQS_BY15_L_P	AG5

DDR2_DIMM_DQ_BY9_B5		J11		DDR2_DIMM_DQS_BY8_L_N	C13

DDR2_DIMM_DQ_BY9_B6		K11		DDR2_DIMM_DQS_BY8_L_P	B13

DDR2_DIMM_DQ_BY9_B7		D11		DDR2_DIMM_DQS_BY9_L_N	K9

DDR2_DIMM_DQ_CB8_15_B0 20		P5		DDR2_DIMM_DQS_BY9_L_P	K8

DDR2_DIMM_DQ_CB8_15_B1		N5		DDR2_DIMM_DQS_CB8_15_L_N	R8

DDR2_DIMM_DQ_CB8_15_B2		L6		DDR2_DIMM_DQS_CB8_15_L_P	R7

DDR2_DIMM_DQ_CB8_15_B3		M7

	DDR2 DIMM Miscellaneous Signals

DDR2_DIMM1_CNTL_PAR		G27		DDR2_DIMM3_CNTL_PAR	AA28

DDR2_DIMM1_CNTL_PAR_ERR		H27		DDR2_DIMM3_CNTL_PAR_ERR	AG28

DDR2_DIMM1_NC_019		K24		DDR2_DIMM3_NC_019	AK29

DDR2_DIMM1_NC_102		L24		DDR2_DIMM3_NC_102	AJ29

DDR2_DIMM2_CNTL_PAR		AD26		DDR2_DIMM4_CNTL_PAR	AG8

DDR2_DIMM2_CNTL_PAR_ERR		AD25		DDR2_DIMM4_CNTL_PAR_ERR	AH8

DDR2_DIMM2_NC_019		AK28		DDR2_DIMM4_NC_019	AL10

DDR2_DIMM2_NC_102		AK27		DDR2_DIMM4_NC_102	AE8

R

104	www.xilinx.com	Virtex-5 FPGA ML561 User Guide
		UG199 (v1.2) April 19, 2008

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Xilinx ML561 manual Table A-2FPGA #2 Pinout Signal Name

Contents

Virtex-5 Fpga ML561 Memory Interfaces Development Board UG199 v1.2 April 19Revision History Date Version RevisionTable of Contents Electrical Requirements Appendix B Bill of Materials Appendix C LCD Interface Virtex-5 Fpga ML561 User Guide Additional Documentation Guide ContentsAbout This Guide Additional Support Resources Preface About This GuideConventions TerminologyTypographical Online DocumentVirtex-5 Fpga ML561 User Guide Introduction About the Virtex-5 Fpga ML561 Memory Interfaces Tool KitVirtex-5 Fpga ML561 Memory Interfaces Development Board IntroductionVirtex-5 Fpga ML561 Memory Interfaces Development Board 2Virtex-5 Fpga ML561 Development BoardIntroduction Documentation and Reference Design CD Initial Board Check Before Applying PowerGetting Started Applying Power to the Board Getting StartedHardware Description Hardware Overview1ML561 XC5VLX50T-FFG1136 Board Placement Diagram Hardware DescriptionHardware Overview MemoriesDDR400 Sdram Components DDR2 Sdram Components Rldram II DevicesMemory Details Memory DetailsDDR400 and DDR2 Component Memories DDR1RAS,CAS,WEN, DDR1CKE DDR2ODT10, DDR2RAS,CAS,WENDDR2 Sdram Dimm DDR2DIMMRAS,CAS,WE,RESETN DimmDDR2DIMM15CNTLPAR DDR2DIMM15CNTLPARERRQdrii and Rldram II Memories QDR2R,W,DLLOFFN Clocks External InterfacesRS-232 MHz Clock MHz Lvpecl ClockSMA Clock DIP Switch User I/OsMHz System ACE Controller Oscillator GTP ClocksSeven-Segment Display Signal Mapping Seven-Segment DisplaysLight Emitting Diodes LEDs PushbuttonsSoft Touch Probe Points Power On or Off Slide SwitchPower Measurement Header Liquid Crystal Display Connector Power Regulation Power RegulationPower Distribution Voltage Regulators 10PTH05010 Voltage Regulator16Manual Voltage Margining Output VoltageBoard Design Considerations Board Design Considerations 11ML561 Revision a PCB Stack-Up19ML561 Revision a PCB Controlled Impedance TOPPower Consumption Electrical RequirementsTotal Available Power Power Consumed DDR400 Component InterfaceTotal Power Consumed CurrentPower Modules Capacity Stack-Up 2Power Planes Voltage Regulator Module VRM PartElectrical Requirements Power Consumption 3ML561 Power Plane CapacitiesCurrent Power Excess Device Description Quantity Power Consumed by Power PlaneElectrical Requirements 3ML561 Power Plane Capacities Total Power Consumed 53.2 Power Consumption 3ML561 Power Plane CapacitiesCurrent Power Excess Device Description Fpga #21 Fpga Internal Power Budget4ML561 Fpga Power Estimate Summary Signal Integrity Recommendations Termination and Transmission Line Summaries2DDR2 Sdram Dimm Terminations Signal Fpga Driver 5RLDRAM II Terminations Signal HSTLI18HSTLIDCI18 HSTLIIDCI18Signal Integrity Recommendations Configuration Configuration ModesConfiguration 1Configuration Modes Jtag ChainJtag Port Parallel IV Cable PortSystem ACE Interface Configuration ML561 Hardware-Simulation Correlation IntroductionTest Setup ML561 Hardware-Simulation CorrelationTest Setup 1Single Trapezoid Eye Mask DefinitionSignal Integrity Correlation Results 2Two Triangular Eye Mask Definitions for VIH and VILSignal Integrity Correlation Results DDR2 Component Write Operation2DDR2 Component Write Operation Correlation Results Measurement3DIP12 Settings Description Voltage mV Voltage mV Time ns UG199c711071007 5DDR2 Component Read Operation Correlation Results DDR2 Component Read OperationFpga SSTL18IIDCII Time ns UG199c715071107 UG199c717071007 UG199c719071007 DDR2 Dimm Write Operation DDR2 DIMM, 75 Ω ODT8DIP12 Settings Description Noise Margin Overshoot / Undershoot MeasurementUG199c722071107 UG199c724071107 UG199c726071007 UG199c729071007 DDR2 Dimm Read Operation 10DDR2 Dimm Read Operation Correlation Results DVW %UG199c731071107 1800.0 1600.0 1400.0 1200.0 1000.0 UG199c735071007 UG199c737071007 12 Qdrii Write Operation Correlation Results Qdrii Write OperationFpga HSTLI18 800.0 600.0 400.0 200.0 000 Probe 3C7.1 at pin 1200.0 1600.0 UG199c742071107 UG199c744070907 3100.0 2600.0 2100.0 1600.0 1100.0 14QDRII Read Operation Correlation Results Qdrii Read OperationFpga HSTLIDCI18 UG199c749071107 1900.0 1700.0 1500.0 1300.0 1100.0 UG199c753070907 UG199c755070907 Noise Margin Overshoot Operation Summary and RecommendationsSummary and Recommendations 16Summary of Worst-Case SI Characteristics How to Generate a User-Specific Fpga Ibis Model How to Generate a User-Specific Fpga Ibis ModelML561 Hardware-Simulation Correlation Fpga Pinouts Fpga #1 PinoutTable A-1FPGA #1 Pinout Signal Name Fpga #1 Clock and Reset Signals FPGA2TOFPGA1MIITXCLK FPGA3TOFPGA1MIITXCLKFPGA2TOFPGA1MIITXDATA0 FPGA3TOFPGA1MIITXDATA0Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #2 Pinout DDR2DIMM3CK2P DDR2DIMMDQBY0B4DDR2DIMM3CKE0 DDR2DIMMDQBY0B5DDR2DIMMDQBY4B4 DDR2DIMMDQBY7B7DDR2DIMMDQBY4B5 DDR2DIMMDQCB07B0DDR2DIMM5CS0N DDR2DIMMDQBY11B5 DDR2DIMM5CS1NDDR2DIMMDQBY11B6 DDR2DIMM5ODT0 AA9 DDR2DIMMDQBY11B7Table A-2FPGA #2 Pinout Signal Name Fpga #2 Pinout Table A-2FPGA #2 Pinout Signal Name Fpga #2 Clock and Reset SignalsFPGA2DIP0 FPGA2SOFTTOUCHBY1B7FPGA2DIP1 FPGA2SPYHOLEBK15FPGA2TXN0BK120 FPGA2USBCTSN FPGA2TXN1BK120 FPGA2USBDSRNFPGA2TXP0BK120 FPGA2USBDTRN FPGA2TXP1BK120 FPGA2USBRSTNTable A-3FPGA #3 Pinout Signal Name Qdrii Memory Interface Fpga #3 PinoutQDR2DBY0B5 QDR2DBY4B1QDR2DBY0B6 QDR2DBY4B2QDR2DBY7B6 QDR2QBY3B2QDR2DBY7B7 QDR2QBY3B3QDR2QBY6B7 QDR2QBY7B4QDR2QBY6B8 QDR2QBY7B5RLD2DBY0B5 RLD2DMBY23N RLD2DBY0B6 RLD2DQBY0B0 RLD2DBY0B7 RLD2DQBY0B1RLD2DBY0B8 RLD2DQBY0B2 RLD2DBY1B0 RLD2DQBY0B3FPGA3RESETNIN RLD2DQBY3B4 RLD2DQBY3B7 RLD2DQBY3B5 RLD2DQBY3B8 RLD2DQBY3B6CLKTOFPGA3MGTN EXTCLKTOFPGA3N CLKTOFPGA3MGTP EXTCLKTOFPGA3PTable A-3FPGA #3 Pinout Signal Name Bill of Materials Table B-1Bill of MaterialsAppendix B Bill of Materials Table B-1Bill of Materials 4A LDOVirtex-5 Fpga ML561 User Guide 117 Appendix B Bill of Materials Display Hardware Design LCD InterfaceGeneral Appendix C LCD Interface Hardware Schematic DiagramTable C-1Display Controller Specifications Parameter Hardware Schematic Diagram Peripheral Device KS071364128EFCBC-XLP Block Diagram Controller Operation Table C-2 LCD Panel124 Controller LCD Panel Connections Controller Power Supply Circuits Figure C-5Power Supply CircuitsOperation Example of the 64128EFCBC-3LP Figure C-6LCD Controller Initialization FlowOFF Reference Voltage Parameter α Table C-4Resistor Value SettingsTable C-5 Reference Voltage Parameters Instruction Set Table C-6Display InstructionsHardware Schematic Diagram Table C-6Display Instructions Set page addressAppendix C LCD Interface Table C-6Display Instructions EONRead/Write Characteristics 6800 Mode ERDLCD Panel Used in Full Graphics Mode Design ExamplesLCD Panel Used in Character Mode Display Command ByteDisplay Data Byte Figure C-10Block RAM Organization Figure C-11LCD Character Generator Controller Array Connector Numbering C D E F G H140