Xilinx ML561 manual DDR2 Component Read Operation, Fpga SSTL18IIDCII

R

Signal Integrity Correlation Results

DDR2 Component Read Operation

This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from the DDR2 memory component (U12) to FPGA1 (U7) measured at 333 MHz (667 Mb/s), where the unit interval (UI) = 1.5 ns.

U12.D3 TL2 TL3 TL4 TL8 TL9 TL6 TL5 TL1 U7.P25

	28.5 ohms
MT47H64M8CB-3	3.579 ps
DQ3	0.022 in
	DDR2_DQ_BY2_B3

71.0 ohms		49.0 ohms
27.482 ps		24.721 ps
AutoPadstk_3		0.164 in
		DDR2_DQ_BY2_B3
DDR2_D…
	DDR2_D…		C9
22.9 fF		22.9 fF		500.0 fF

	58.3 ohms		49.1 ohms	49.1 ohms
	25.244 ps		47.132 ps	445.560 ps
	AutoPadstk_19		0.302 in	2.852 in
			DDR2_DQ_BY2_B3 DDR2_DQ_BY2_B3
DDR2_D…		DDR2_D…
	58.1 fF		140.8 fF

21.2ohms

1.000 ps AutoPadstk_3

DDR2_D…

C7

365.6 fF 500.0 fF

28.5 ohms	Virtex-5 FPGA
4.473 ps
0.028 in	DDR2_DQ_BY2_B3

DDR2_DQ_BY2_B3

DDR2_D…

22.9 fF

UG199_c7_12_071907

Figure 7-12:Post-Layout IBIS Schematics of the DDR2 Component Read Data Bit (DDR2_DQ_BY2_B3)

Table 7-4:Circuit Elements of DDR2 Component Read Data Bit (DDR2_DQ_BY2_B3)

		Element		Designation			Description
	Driver			U12.D3			DDR2 Memory
	Receiver			U7.P25			FPGA SSTL18_II_DCI_I
	Probe Point			C7			Via under FPGA1
	PCB Termination			None			DCI at receiver
	Trace Length			TL 2, 4, 9, 6, 1			3.37 inches
Table 7-5:DDR2 Component Read Operation Correlation Results
				ISI		Noise Margin		Overshoot /
Measurement		DVW (% UI)			(VIH + VIL) = Total			Undershoot Margin
				(% UI)
						(% of VREF)		(% of VREF)
Hardware at probe point		1.28 ns	(70 + 110) = 180 ps		(423 + 416) = 839 mV			(400 +400) = 800 mV
		(85%)	(12%)			(83.1%)		(79.1%)
Simulation correlation		1.28 ns	(132 + 91) = 223 ps		(406 +439) = 845 mV			(279 +277) = 556 mV
slow-weak corner		(85%)	(14.9%)			(83.8%)		(61.9%)
Correlation Delta:		0 ps		43 ps			6 mV	244 mV
HW vs. Simulation		(0.0%)	(2.9%)			(0.7%)		(17.2%)
Extrapolation at IOB		1.29 ns	(96 + 82) = 178 ps		(418 + 449) = 867 mV			(304 +265) = 569 mV
slow-weak corner		(86%)	(11.9%)			(96.3%)		(63.1%)
Extrapolation at IOB		1.32 ns	(29 + 67) = 96 ps		(455 +435) = 890 mV			(167 +182) = 349 mV
fast-strong corner		(88%)	(6.7%)			(98.9%)		(38.9%)

To perform hardware measurements for a Read operation that is not interrupted by a Write or a Refresh operation, the testbench on FPGA1 is controlled by the following DIP switch (SW2) setting:

•DIP[1:2] = 2’b10 – Write once, then Read only, Refresh disabled

Virtex-5 FPGA ML561 User Guide www.xilinx.com 65

UG199 (v1.2) April 19, 2008