Xilinx ML561 DDR2 Component Write Operation, Signal Integrity Correlation Results, Measurement

R

Signal Integrity Correlation Results

DDR2 Component Write Operation

This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from FPGA1 (U7) to the DDR2 memory component (U12) measured at 333 MHz (667 Mb/s), where the unit interval (UI) = 1.5 ns.

	28.5 ohms		49.0 ohms		49.1 ohms	49.1 ohms		28.5 ohms
	3.579 ps	71.0 ohms	24.721 ps	58.3 ohms	47.132 ps	445.560 ps	21.2 ohms	4.473 ps
U12.D3	0.022 in	27.482 ps	0.164 in	25.244 ps	0.302 in	2.852 in	1.000 ps	0.028 in	U7.P25
	DDR2_DQ_BY2_B3	AutoPadstk_3	DDR2_DQ_BY2_B3	AutoPadstk_19	DDR2_DQ_BY2_B3	DDR2_DQ_BY2_B3	AutoPadstk_3	DDR2_DQ_BY2_B3

TL2

MT47H32M16CC_… DQ11

TL3

DDR2_D…

22.9 fF

TL4

DDR2_D… C9

22.9 fF 500.0 fF

TL8

DDR2_D…

58.1 fF

TL9TL6

DDR2_D…

140.8 fF

TL5 TL1

Virtex-5 FPGA

DDR2_DQ_BY2_B3

DDR2_D…

DDR2_D… C7

22.9 fF

365.6 fF 500.0 fF

UG199_c7_03_071907

Figure 7-3:Post-Layout IBIS Schematics of DDR2 Component Write Data Bit (DDR2_DQ_BY2_B3)

Table 7-1:Circuit Elements of DDR2 Component Write Data Bit (DDR2_DQ_BY2_B3)

	Element		Designation				Description
	Driver		U7.P25			FPGA SSTL18_II_DCI_O
	Receiver		U12.D3			DDR2 Memory, 75 Ω ODT
	Probe Point		C9			Via under the memory device
	PCB Termination		None			ODT75 at load
	Trace Length		TL 2, 4, 9, 6, 1			3.37 inches
Table 7-2:DDR2 Component Write Operation Correlation Results
	DVW(1)	ISI			Noise Margin		Overshoot / Undershoot
Measurement				(VIH, + VIL) = Total			Margin
	(%UI)	(% UI)
					(% of VREF)		(% of VREF)
Hardware at probe	1.18 ns	(80 + 80) = 160 ps		(274 + 384) = 658 mV			(550 + 470) = 1020 mV
point	(78.7%)	(10.7%)			(73.1%)		(113.3%)
Simulation correlation	1.22 ns	(77 + 36) = 113 ps		(294 + 266) = 560 mV			(461 + 490) = 951 mV
slow-weak corner	(81.3%)	(7.5%)			(62.2%)		(105.7%)
Correlation Delta:	40 ps	47 ps			98 mV		69 mV
HW vs. Simulation	(2.6%)	(3.2%)			(10.9%)		(7.6%)
Extrapolation at IOB	1.27 ns	(91 + 36) = 127 ps		(300 + 270) = 570 mV			(469 + 501) = 970 mV
slow-weak corner	(84%)	(8.5%)			(63.3%)		(107.8%)
Extrapolation at IOB	1.39 ns	(34 + 20) = 54 ps		(406 + 351) = 757 mV			(304 + 381) = 685 mV
fast-strong corner	(92%)	(3.7%)			(84.1%)		(76.1%)

Notes:

1. DVW = Data Valid Window, ISI = Inter-Symbol Interference

Virtex-5 FPGA ML561 User Guide www.xilinx.com 59

UG199 (v1.2) April 19, 2008