Xilinx ML561 User I/Os, MHz System ACE Controller Oscillator, GTP Clocks, General-Purpose Headers

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External Interfaces

Table 3-12:FPGA Slow Clock Sources

FPGA Signal Name

1FPGA1_LOW_FREQ_CLK

2FPGA2_LOW_FREQ_CLK

3FPGA3_LOW_FREQ_CLK

33 MHz System ACE Controller Oscillator

Asingle-ended 33 MHz Epson SG-8002CA oscillator is provided on the board (Y3) as a clock source for System ACE functionality.

GTP Clocks

Two SMA connectors are provided for the input of an off-board differential clock (J16 and J21). A differential clock buffer (ICS8543BG) is used on the board (U20) to generate four LVDS copies of the differential clock signal, two for FPGA #1, one for FPGA #2, and one for FPGA #3.

A header is used to select between a clock forwarded by the GTP or from the external clock source used to provide a clock to the FPGA logic.

User I/Os

This subsection describes the devices that connect to the User I/Os of the ML561 board. These I/Os are provided to ease hardware development using the ML561.

General-Purpose Headers

The 16-pin test headers are surface mounted, one per FPGA. Of the two bytes of test signals, traces are matched for signals within a byte.

Table 3-13: Test Headers

Header Signal Description	Location	Header Pin #
FPGA1_TEST_HDR_BY0_B[0:7]	P20 (TEST1)	Odd pins: 1, 3, 5, 7, 9, 11, 13, 15
FPGA1_TEST_HDR_BY1_B[0:7]	P20 (TEST1)	Even pins: 2, 4, 6, 8, 10, 12, 14, 16
FPGA2_TEST_HDR_BY0_B[0:7]	P21 (TEST2)	Odd pins: 1, 3, 5, 7, 9, 11, 13, 15
FPGA2_TEST_HDR_BY1_B[0:7]	P21 (TEST2)	Even pins: 2, 4, 6, 8, 10, 12, 14, 16
FPGA3_TEST_HDR_BY0_B[0:7]	P93 (TEST3)	Odd pins: 1, 3, 5, 7, 9, 11, 13, 15
FPGA3_TEST_HDR_BY1_B[0:7]	P93 (TEST3)	Even pins: 2, 4, 6, 8, 10, 12, 14, 16

DIP Switch

One four-position DIP switch per FPGA (for a total of three) is available to externally pull up or pull down a signal on the FPGA. This can be used to manually set values used by the design running on the FPGA.

Virtex-5 FPGA ML561 User Guide www.xilinx.com 29

UG199 (v1.2) April 19, 2008