Appendix C: LCD Interface
R
Design Examples
LCD Panel Used in Full Graphics Mode
The LCD controller RAM has eight
One
One block RAM can be used to store one complete pixel view of the LCD panel. There is enough space left for commands.
The ninth bit in the block RAM indicates whether the data in the block RAM is real data to be displayed or is a command for the controller.
The interface to the LCD panel is slow. The E signal can be used as the controller clock signal. This signal has a minimum cycle time of 400 ns for displaying 8 bits (equal to 8 dots) on the LCD. One full page of the display takes up to 132 x 400 ns = 52.8 μs. Updating the full display takes 52.8μs x 8 = 423μs.
If using the dual port and data width capabilities of the block RAM, then writes to the block RAM can be 32 bits (+4 control bits), and reads from the block RAM on the LCD side can be 8 bits (1 control bit). An entire LCD page is updated in 33 write operations.
The interface on the LCD panel side sequentially reads the block RAM, and thus, updates the screen contiguously (like a television screen). The controller (microcontroller or other) side of the block RAM can be written at any time.
The write operation happens on the rising edge of the clock and the read (LCD update) happens on the falling edge of the clock. Normally write and read operations at the same address give corrupt read data when the read and write clock edges do not respect the
A state machine provides correct timing of the signals on the LCD panel side. The panel can be used in
At first, the block RAM must be initialized with some data (instructions to the LCD) to make the LCD operate correctly. Figure
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| UG199 (v1.2) April 19, 2008 |