Virtex-5 Fpga ML561 Memory Interfaces Development Board
UG199 v1.2 April 19
Revision History
Date Version Revision
Table of Contents
Electrical Requirements
Appendix B Bill of Materials Appendix C LCD Interface
Virtex-5 Fpga ML561 User Guide
About This Guide
Guide Contents
Additional Documentation
Additional Support Resources
Preface About This Guide
Typographical
Conventions
Terminology
Online Document
Virtex-5 Fpga ML561 User Guide
Introduction
About the Virtex-5 Fpga ML561 Memory Interfaces Tool Kit
Virtex-5 Fpga ML561 Memory Interfaces Development Board
Introduction
Virtex-5 Fpga ML561 Memory Interfaces Development Board
2Virtex-5 Fpga ML561 Development Board
Introduction
Getting Started
Initial Board Check Before Applying Power
Documentation and Reference Design CD
Applying Power to the Board
Getting Started
Hardware Description
Hardware Overview
1ML561 XC5VLX50T-FFG1136 Board Placement Diagram
Hardware Description
DDR400 Sdram Components
Memories
Hardware Overview
DDR2 Sdram Components
Rldram II Devices
DDR400 and DDR2 Component Memories
Memory Details
Memory Details
DDR1RAS,CAS,WEN, DDR1CKE
DDR2ODT10, DDR2RAS,CAS,WEN
DDR2 Sdram Dimm
DDR2DIMM15CNTLPAR
DDR2DIMMRAS,CAS,WE,RESETN
Dimm
DDR2DIMM15CNTLPARERR
Qdrii and Rldram II Memories
QDR2R,W,DLLOFFN
RS-232
External Interfaces
Clocks
SMA Clock
MHz Lvpecl Clock
MHz Clock
MHz System ACE Controller Oscillator
DIP Switch
User I/Os
GTP Clocks
Light Emitting Diodes LEDs
Seven-Segment Display Signal Mapping
Seven-Segment Displays
Pushbuttons
Power Measurement Header
Power On or Off Slide Switch
Soft Touch Probe Points
Liquid Crystal Display Connector
Power Distribution
Power Regulation
Power Regulation
Voltage Regulators
10PTH05010 Voltage Regulator
16Manual Voltage Margining
Output Voltage
Board Design Considerations
Board Design Considerations
11ML561 Revision a PCB Stack-Up
19ML561 Revision a PCB Controlled Impedance
TOP
Power Consumption
Electrical Requirements
Total Power Consumed
Total Available Power
Power Consumed DDR400 Component Interface
Current
Power Modules Capacity
Electrical Requirements
2Power Planes Voltage Regulator Module VRM Part
Stack-Up
Current Power Excess Device Description Quantity
Power Consumption
3ML561 Power Plane Capacities
Power Consumed by Power Plane
Electrical Requirements 3ML561 Power Plane Capacities
Current Power Excess Device Description
Power Consumption 3ML561 Power Plane Capacities
Total Power Consumed 53.2
4ML561 Fpga Power Estimate Summary
Fpga Internal Power Budget
Fpga #21
Signal Integrity Recommendations
Termination and Transmission Line Summaries
2DDR2 Sdram Dimm Terminations Signal Fpga Driver
HSTLIDCI18
5RLDRAM II Terminations Signal
HSTLI18
HSTLIIDCI18
Signal Integrity Recommendations
Configuration
Configuration Modes
Jtag Port
Configuration 1Configuration Modes
Jtag Chain
Parallel IV Cable Port
System ACE Interface
Configuration
ML561 Hardware-Simulation Correlation
Introduction
Test Setup
ML561 Hardware-Simulation Correlation
Test Setup
1Single Trapezoid Eye Mask Definition
Signal Integrity Correlation Results
2Two Triangular Eye Mask Definitions for VIH and VIL
2DDR2 Component Write Operation Correlation Results
Signal Integrity Correlation Results
DDR2 Component Write Operation
Measurement
3DIP12 Settings Description
Voltage mV
Voltage mV
Time ns
UG199c711071007
Fpga SSTL18IIDCII
DDR2 Component Read Operation
5DDR2 Component Read Operation Correlation Results
Time ns
UG199c715071107
UG199c717071007
UG199c719071007
DDR2 Dimm Write Operation
DDR2 DIMM, 75 Ω ODT
8DIP12 Settings Description
Noise Margin Overshoot / Undershoot Measurement
UG199c722071107
UG199c724071107
UG199c726071007
UG199c729071007
DDR2 Dimm Read Operation
10DDR2 Dimm Read Operation Correlation Results DVW %
UG199c731071107
1800.0 1600.0 1400.0 1200.0 1000.0
UG199c735071007
UG199c737071007
Fpga HSTLI18
Qdrii Write Operation
12 Qdrii Write Operation Correlation Results
800.0 600.0 400.0 200.0 000 Probe 3C7.1 at pin 1200.0 1600.0
UG199c742071107
UG199c744070907
3100.0 2600.0 2100.0 1600.0 1100.0
Fpga HSTLIDCI18
Qdrii Read Operation
14QDRII Read Operation Correlation Results
UG199c749071107
1900.0 1700.0 1500.0 1300.0 1100.0
UG199c753070907
UG199c755070907
Summary and Recommendations
Summary and Recommendations
Noise Margin Overshoot Operation
16Summary of Worst-Case SI Characteristics
How to Generate a User-Specific Fpga Ibis Model
How to Generate a User-Specific Fpga Ibis Model
ML561 Hardware-Simulation Correlation
Fpga Pinouts
Fpga #1 Pinout
Table A-1FPGA #1 Pinout Signal Name
Fpga #1 Clock and Reset Signals
FPGA2TOFPGA1MIITXDATA0
FPGA2TOFPGA1MIITXCLK
FPGA3TOFPGA1MIITXCLK
FPGA3TOFPGA1MIITXDATA0
Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name
Fpga #2 Pinout
DDR2DIMM3CKE0
DDR2DIMM3CK2P
DDR2DIMMDQBY0B4
DDR2DIMMDQBY0B5
DDR2DIMMDQBY4B5
DDR2DIMMDQBY4B4
DDR2DIMMDQBY7B7
DDR2DIMMDQCB07B0
DDR2DIMMDQBY11B6
DDR2DIMM5CS0N
DDR2DIMMDQBY11B5 DDR2DIMM5CS1N
DDR2DIMM5ODT0 AA9 DDR2DIMMDQBY11B7
Table A-2FPGA #2 Pinout Signal Name
Fpga #2 Pinout Table A-2FPGA #2 Pinout Signal Name
Fpga #2 Clock and Reset Signals
FPGA2DIP1
FPGA2DIP0
FPGA2SOFTTOUCHBY1B7
FPGA2SPYHOLEBK15
FPGA2TXP0BK120 FPGA2USBDTRN
FPGA2TXN0BK120 FPGA2USBCTSN
FPGA2TXN1BK120 FPGA2USBDSRN
FPGA2TXP1BK120 FPGA2USBRSTN
Table A-3FPGA #3 Pinout Signal Name Qdrii Memory Interface
Fpga #3 Pinout
QDR2DBY0B6
QDR2DBY0B5
QDR2DBY4B1
QDR2DBY4B2
QDR2DBY7B7
QDR2DBY7B6
QDR2QBY3B2
QDR2QBY3B3
QDR2QBY6B8
QDR2QBY6B7
QDR2QBY7B4
QDR2QBY7B5
RLD2DBY0B8 RLD2DQBY0B2 RLD2DBY1B0
RLD2DBY0B5 RLD2DMBY23N RLD2DBY0B6 RLD2DQBY0B0
RLD2DBY0B7 RLD2DQBY0B1
RLD2DQBY0B3
CLKTOFPGA3MGTN EXTCLKTOFPGA3N
FPGA3RESETNIN
RLD2DQBY3B4 RLD2DQBY3B7 RLD2DQBY3B5 RLD2DQBY3B8 RLD2DQBY3B6
CLKTOFPGA3MGTP EXTCLKTOFPGA3P
Table A-3FPGA #3 Pinout Signal Name
Bill of Materials
Table B-1Bill of Materials
Appendix B Bill of Materials Table B-1Bill of Materials
4A LDO
Virtex-5 Fpga ML561 User Guide 117
Appendix B Bill of Materials
General
LCD Interface
Display Hardware Design
Table C-1Display Controller Specifications Parameter
Hardware Schematic Diagram
Appendix C LCD Interface
Hardware Schematic Diagram
Peripheral Device KS0713
64128EFCBC-XLP Block Diagram
Controller Operation
Table C-2 LCD Panel
124
Controller LCD Panel Connections
Controller Power Supply Circuits
Figure C-5Power Supply Circuits
Operation Example of the 64128EFCBC-3LP
Figure C-6LCD Controller Initialization Flow
OFF
Table C-5 Reference Voltage Parameters
Table C-4Resistor Value Settings
Reference Voltage Parameter α
Instruction Set
Table C-6Display Instructions
Hardware Schematic Diagram Table C-6Display Instructions
Set page address
Appendix C LCD Interface Table C-6Display Instructions
EON
Read/Write Characteristics 6800 Mode
ERD
LCD Panel Used in Full Graphics Mode
Design Examples
LCD Panel Used in Character Mode
Display Command Byte
Display Data Byte
Figure C-10Block RAM Organization
Figure C-11LCD Character Generator Controller
Array Connector Numbering
C D E F G H
140