Xilinx ML561 manual Figure C-11LCD Character Generator Controller

Appendix C: LCD Interface

R

Figure C-11shows a block diagram of the LCD character generator controller. Character data is latched and then shifted left three positions. This shifted value is the start byte for a counter that outputs an address to the block RAM. The result is a stream of bytes representing a character for the display.

A small second counter determines when a new character is loaded into the block RAM address counter.

Position

Register

Page

8

DesRst

Counter A

0

Data

DI

8

8

DataIn

11

11

1

Addr

DO

8

Ena

Ena

E

3

E

Rst

L

DesRst

Ssr

RAMB16_S9

Display

Clk

Clk

We

Register

DesRst

DesRst

Clk

Clk

E

Load

LUT-ROM

Counter B

TC

Display

DesRst

Initialization

Clk

Count to 8.

Stop both counters at TC.

Rst

RS

DesRst

Send character position and

RW

line to the LCD.

Ena

State Machine

E

Load new value in counter A.

Clk

Switch to character ROM.

Enable counters.

UG199_C_11_050106

Figure C-11:LCD Character Generator Controller

A state machine manages the processing order.

A minimum cycle time of 400 ns on the E signal used as a reference. The 200 MHz system clock frequency is used as reference system clock. One E cycle uses at least 80 system clock cycles when the design is running at 200 MHz. The E pulse is part of the state machine, and the design only depends on the system clock. Timing is met as long as the system clock does not exceed 200 MHz.

This design can be adapted easily to fit the MicroBlaze™ or PPC405 CoreConnect bus system.

138 www.xilinx.com Virtex-5 FPGA ML561 User Guide

UG199 (v1.2) April 19, 2008