DDR1RAS,CAS,WEN, DDR1CKE, DDR2ODT10, DDR2RAS,CAS,WEN | Xilinx ML561

Chapter 3: Hardware Description

Table 3-3describes all signals associated with DDR400 Component memories.

R

Table 3-3:DDR400 Component Signal Summary

Board Signal Name(s)	Bits	Description

DDR1_A[13:0]	14	DDR400 Component Address

DDR1_CK[2:1]_[P,N]	4	DDR400 Component Differential Clock

DDR1_[RAS,CAS,WE]_N, DDR1_CKE,	12	DDR400 Component Control Signals
DDR1_BA[1:0], DDR1_BY[0_1,2_3]_CS_N,
DDR1_DM_BY[3:0]

DDR1_DQ_BY0_B[7:0], DDR1_DQS_BY0_P	9	DDR400 Data and Strobe: Byte 0

DDR1_DQ_BY1_B[7:0], DDR1_DQS_BY1_P	9	DDR400 Data and Strobe: Byte 1

DDR1_DQ_BY2_B[7:0], DDR1_DQS_BY2_P	9	DDR400 Data and Strobe: Byte 2

DDR1_DQ_BY3_B[7:0], DDR1_DQS_BY3_P	9	DDR400 Data and Strobe: Byte 3

Notes:

1. DDR1_CKE signal has a weak 4.7KΩ pull-down resistor to meet the memory power-up requirements.

Table 3-4describes all signals associated with DDR2 Component memories. For a complete list of FPGA #1 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”

Table 3-4:DDR2 Component Signal Summary

Board Signal Name(s)	Bits	Description

DDR2_A[12:0]	13	DDR2 Component Address

DDR2_CK[1:0]_[P,N]	4	DDR2 Component Differential
		Clock

DDR2_ODT[1:0], DDR2_[RAS,CAS,WE]_N,	14	DDR2 Component Control Signals
DDR2_CKE, DDR2_BA[1:0], DDR2_CS[1:0]_N,
DDR2_DM_BY[3:0]

DDR2_DQ_BY0_B[7:0], DDR2_DQS_BY0_[P,N]	10	DDR2 Data and Strobe: Byte 0

DDR2_DQ_BY1_B[7:0], DDR2_DQS_BY1_[P,N]	10	DDR2 Data and Strobe: Byte 1

DDR2_DQ_BY2_B[7:0], DDR2_DQS_BY2_[P,N]	10	DDR2 Data and Strobe: Byte 2

DDR2_DQ_BY3_B[7:0], DDR2_DQS_BY3_[P,N]	10	DDR2 Data and Strobe: Byte 3

Notes:

1.DDR2_CKE and DDR2_ODT[1:0] signals have a weak 4.7KΩ pull-down resistor to meet the memory power-up requirements.

XAPP851, DDR SDRAM Controller Using Virtex-5 FPGA Devices, XAPP858, High- Performance DDR2 SDRAM Interface in Virtex-5 Devices, and the corresponding demos are included on the CD shipped with the ML561 Tool Kit. For a complete list of FPGA #1 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”

22	www.xilinx.com	Virtex-5 FPGA ML561 User Guide
		UG199 (v1.2) April 19, 2008

Image 22

Xilinx ML561 manual DDR1RAS,CAS,WEN, DDR1CKE, DDR2ODT10, DDR2RAS,CAS,WEN

Contents

Virtex-5 Fpga ML561 Memory Interfaces Development Board UG199 v1.2 April 19 Revision History Date Version Revision Table of Contents Electrical Requirements Appendix B Bill of Materials Appendix C LCD Interface Virtex-5 Fpga ML561 User Guide About This Guide Guide ContentsAdditional Documentation Additional Support Resources Preface About This Guide Typographical ConventionsTerminology Online Document Virtex-5 Fpga ML561 User Guide Introduction About the Virtex-5 Fpga ML561 Memory Interfaces Tool Kit Virtex-5 Fpga ML561 Memory Interfaces Development Board Introduction Virtex-5 Fpga ML561 Memory Interfaces Development Board 2Virtex-5 Fpga ML561 Development Board Introduction Getting Started Initial Board Check Before Applying PowerDocumentation and Reference Design CD Applying Power to the Board Getting Started Hardware Description Hardware Overview 1ML561 XC5VLX50T-FFG1136 Board Placement Diagram Hardware Description DDR400 Sdram Components MemoriesHardware Overview DDR2 Sdram Components Rldram II Devices DDR400 and DDR2 Component Memories Memory DetailsMemory Details DDR1RAS,CAS,WEN, DDR1CKE DDR2ODT10, DDR2RAS,CAS,WEN DDR2 Sdram Dimm DDR2DIMM15CNTLPAR DDR2DIMMRAS,CAS,WE,RESETNDimm DDR2DIMM15CNTLPARERR Qdrii and Rldram II Memories QDR2R,W,DLLOFFN RS-232 External InterfacesClocks SMA Clock MHz Lvpecl ClockMHz Clock MHz System ACE Controller Oscillator DIP SwitchUser I/Os GTP Clocks Light Emitting Diodes LEDs Seven-Segment Display Signal MappingSeven-Segment Displays Pushbuttons Power Measurement Header Power On or Off Slide SwitchSoft Touch Probe Points Liquid Crystal Display Connector Power Distribution Power RegulationPower Regulation Voltage Regulators 10PTH05010 Voltage Regulator 16Manual Voltage Margining Output Voltage Board Design Considerations Board Design Considerations 11ML561 Revision a PCB Stack-Up 19ML561 Revision a PCB Controlled Impedance TOP Power Consumption Electrical Requirements Total Power Consumed Total Available PowerPower Consumed DDR400 Component Interface Current Power Modules Capacity Electrical Requirements 2Power Planes Voltage Regulator Module VRM PartStack-Up Current Power Excess Device Description Quantity Power Consumption3ML561 Power Plane Capacities Power Consumed by Power Plane Electrical Requirements 3ML561 Power Plane Capacities Current Power Excess Device Description Power Consumption 3ML561 Power Plane CapacitiesTotal Power Consumed 53.2 4ML561 Fpga Power Estimate Summary Fpga Internal Power BudgetFpga #21 Signal Integrity Recommendations Termination and Transmission Line Summaries 2DDR2 Sdram Dimm Terminations Signal Fpga Driver HSTLIDCI18 5RLDRAM II Terminations SignalHSTLI18 HSTLIIDCI18 Signal Integrity Recommendations Configuration Configuration Modes Jtag Port Configuration 1Configuration ModesJtag Chain Parallel IV Cable Port System ACE Interface Configuration ML561 Hardware-Simulation Correlation Introduction Test Setup ML561 Hardware-Simulation Correlation Test Setup 1Single Trapezoid Eye Mask Definition Signal Integrity Correlation Results 2Two Triangular Eye Mask Definitions for VIH and VIL 2DDR2 Component Write Operation Correlation Results Signal Integrity Correlation ResultsDDR2 Component Write Operation Measurement 3DIP12 Settings Description Voltage mV Voltage mV Time ns UG199c711071007 Fpga SSTL18IIDCII DDR2 Component Read Operation5DDR2 Component Read Operation Correlation Results Time ns UG199c715071107 UG199c717071007 UG199c719071007 DDR2 Dimm Write Operation DDR2 DIMM, 75 Ω ODT 8DIP12 Settings Description Noise Margin Overshoot / Undershoot Measurement UG199c722071107 UG199c724071107 UG199c726071007 UG199c729071007 DDR2 Dimm Read Operation 10DDR2 Dimm Read Operation Correlation Results DVW % UG199c731071107 1800.0 1600.0 1400.0 1200.0 1000.0 UG199c735071007 UG199c737071007 Fpga HSTLI18 Qdrii Write Operation12 Qdrii Write Operation Correlation Results 800.0 600.0 400.0 200.0 000 Probe 3C7.1 at pin 1200.0 1600.0 UG199c742071107 UG199c744070907 3100.0 2600.0 2100.0 1600.0 1100.0 Fpga HSTLIDCI18 Qdrii Read Operation14QDRII Read Operation Correlation Results UG199c749071107 1900.0 1700.0 1500.0 1300.0 1100.0 UG199c753070907 UG199c755070907 Summary and Recommendations Summary and RecommendationsNoise Margin Overshoot Operation 16Summary of Worst-Case SI Characteristics How to Generate a User-Specific Fpga Ibis Model How to Generate a User-Specific Fpga Ibis Model ML561 Hardware-Simulation Correlation Fpga Pinouts Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #1 Clock and Reset Signals FPGA2TOFPGA1MIITXDATA0 FPGA2TOFPGA1MIITXCLKFPGA3TOFPGA1MIITXCLK FPGA3TOFPGA1MIITXDATA0 Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #2 Pinout DDR2DIMM3CKE0 DDR2DIMM3CK2PDDR2DIMMDQBY0B4 DDR2DIMMDQBY0B5 DDR2DIMMDQBY4B5 DDR2DIMMDQBY4B4DDR2DIMMDQBY7B7 DDR2DIMMDQCB07B0 DDR2DIMMDQBY11B6 DDR2DIMM5CS0NDDR2DIMMDQBY11B5 DDR2DIMM5CS1N DDR2DIMM5ODT0 AA9 DDR2DIMMDQBY11B7 Table A-2FPGA #2 Pinout Signal Name Fpga #2 Pinout Table A-2FPGA #2 Pinout Signal Name Fpga #2 Clock and Reset Signals FPGA2DIP1 FPGA2DIP0FPGA2SOFTTOUCHBY1B7 FPGA2SPYHOLEBK15 FPGA2TXP0BK120 FPGA2USBDTRN FPGA2TXN0BK120 FPGA2USBCTSNFPGA2TXN1BK120 FPGA2USBDSRN FPGA2TXP1BK120 FPGA2USBRSTN Table A-3FPGA #3 Pinout Signal Name Qdrii Memory Interface Fpga #3 Pinout QDR2DBY0B6 QDR2DBY0B5QDR2DBY4B1 QDR2DBY4B2 QDR2DBY7B7 QDR2DBY7B6QDR2QBY3B2 QDR2QBY3B3 QDR2QBY6B8 QDR2QBY6B7QDR2QBY7B4 QDR2QBY7B5 RLD2DBY0B8 RLD2DQBY0B2 RLD2DBY1B0 RLD2DBY0B5 RLD2DMBY23N RLD2DBY0B6 RLD2DQBY0B0RLD2DBY0B7 RLD2DQBY0B1 RLD2DQBY0B3 CLKTOFPGA3MGTN EXTCLKTOFPGA3N FPGA3RESETNINRLD2DQBY3B4 RLD2DQBY3B7 RLD2DQBY3B5 RLD2DQBY3B8 RLD2DQBY3B6 CLKTOFPGA3MGTP EXTCLKTOFPGA3P Table A-3FPGA #3 Pinout Signal Name Bill of Materials Table B-1Bill of Materials Appendix B Bill of Materials Table B-1Bill of Materials 4A LDO Virtex-5 Fpga ML561 User Guide 117 Appendix B Bill of Materials General LCD InterfaceDisplay Hardware Design Table C-1Display Controller Specifications Parameter Hardware Schematic DiagramAppendix C LCD Interface Hardware Schematic Diagram Peripheral Device KS0713 64128EFCBC-XLP Block Diagram Controller Operation Table C-2 LCD Panel 124 Controller LCD Panel Connections Controller Power Supply Circuits Figure C-5Power Supply Circuits Operation Example of the 64128EFCBC-3LP Figure C-6LCD Controller Initialization Flow OFF Table C-5 Reference Voltage Parameters Table C-4Resistor Value SettingsReference Voltage Parameter α Instruction Set Table C-6Display Instructions Hardware Schematic Diagram Table C-6Display Instructions Set page address Appendix C LCD Interface Table C-6Display Instructions EON Read/Write Characteristics 6800 Mode ERD LCD Panel Used in Full Graphics Mode Design Examples LCD Panel Used in Character Mode Display Command Byte Display Data Byte Figure C-10Block RAM Organization Figure C-11LCD Character Generator Controller Array Connector Numbering C D E F G H 140