Xilinx manual Electrical Requirements 3ML561 Power Plane Capacities

Chapter 4: Electrical Requirements

Table 4-3:ML561 Power Plane Capacities (Continued)

R

		Voltage	Current	Power	Excess
Device Description	Quantity				Power	Source
		(V)	(mA)	(W)	(W)
SSTL18 FPGA Power Plane (1.8V)	1	1.8	15000	27.0	17.5	TI PTH05010 15A Module Data
Capacity						Sheet
DDR2 x16 Memory	2	1.8	250	0.9		Micron DDR2 Component Data
						Sheet
DDR2 DIMM	2	1.8	1755	6.3		Micron DDR2 DIMM Data Sheet
SSTL18_Mem Power Plane (1.8V)	1	1.8	6000	10.8	3.6	TI PTH05010 15A Module Data
Capacity						Sheet
DDR2 Comp VTT Termination	25	1.2	16	0.5		Addr/Cntl: ± 603 mV swing
						around VTT
DDR2 DIMM VTT Termination	160	1.2	16	3.1		All signals: ± 603 mV swing
						around VTT
SSTL18 _VREF Power Plane (0.9V)	1	0.9	3000	2.7	-0.9	Fairchild FN6555 Data Sheet
XC5VLX50T-FFG1136: FPGA #1	1	2.5	609	1.5		Xilinx Power Estimator
(DDR400, DDR2)
XC5VLX50T-FFG1136: FPGA #2	1	2.5	218	0.5		Xilinx Power Estimator
(DDR2 DIMM)
XC5VLX50T-FFG1136: FPGA #3	1	2.5	435	1.1		Xilinx Power Estimator
(QDRII and RLDRAM II)
Differential Clock Buffer	2	2.5	115	0.8		ICS853006 Data Sheet
200 MHz Osc	1	2.5	30	0.1		Epson EG2121CA Data Sheet
2.5V Power Plane Capacity	1	2.5	15000	37.5	34.1	TI PTH05010 15A Module Data
						Sheet
XC5VLX50T-FFG1136: FPGA #1	1	2.6	950	2.5		Xilinx Power Estimator
(DDR400)
SSTL2_FPGA Power Plane (2.6V)	1	2.6	15000	39.0	36.5	TI PTH05010 15A Module Data
Capacity						Sheet
DDR x16 Memory	2	2.6	210	1.1		Micron DDR Component Data
						Sheet
SSTL2_Mem Power Plane (2.6V)	1	2.6	6000	15.6	14.5	TI PTH05010 15A Module Data
Capacity						Sheet
DDR Comp VTT Termination	60	1.2	16	1.2		All signals. ± 608 mV swing
						around VTT
SSTL2 _VREF Power Plane (1.3V)	1	1.3	3000	3.9	2.7	Fairchild FN6555 Data Sheet
Clock Buffer	1	3.3	23	0.1		ICS8304 Data Sheet

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		UG199 (v1.2) April 19, 2008