Fpga #3 Pinout | Xilinx ML561 specs

Appendix A: FPGA Pinouts

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FPGA #3 Pinout

Table A-3lists the connections for FPGA #3 (U34).

Table A-3:FPGA #3 Pinout

Signal Name	Pin		Signal Name	Pin

	QDRII Memory Interface

QDR2_CK_BY0_3_N	K34		QDR2_SA11	AB26

QDR2_CK_BY0_3_P	G28		QDR2_SA12	AB25

QDR2_CK_BY0_3_P	L34		QDR2_SA13	AA24

QDR2_CK_BY4_7_N	AJ34		QDR2_SA14	Y24

QDR2_CK_BY4_7_P	AA31		QDR2_SA15	AC27

QDR2_CK_BY4_7_P	AH34		QDR2_SA16	AB27

QDR2_CQ_BY0_3_N	E26		QDR2_SA17	AA26

QDR2_CQ_BY0_3_P	K33		QDR2_SA2	AJ27

QDR2_CQ_BY4_7_N	AA29		QDR2_SA3	AK26

QDR2_CQ_BY4_7_P	AD32		QDR2_SA4	AF28

QDR2_DLL_OFF_N	AK27		QDR2_SA5	AE28

QDR2_K_BY0_3_N	F28		QDR2_SA6	AH28

QDR2_K_BY0_3_P	E28		QDR2_SA7	AG28

QDR2_K_BY4_7_N	AC30		QDR2_SA8	AA28

QDR2_K_BY4_7_P	AB30		QDR2_SA9	AB28

QDR2_LB_BK11	P32		QDR2_W_N	AH27

QDR2_LB_BK11	P34		QDR2_BW_BY0_N	M32

QDR2_LB_BK13	AE34		QDR2_BW_BY1_N	L33

QDR2_LB_BK13	AJ32		QDR2_BW_BY2_N	L28

QDR2_LB_BK17	AE29		QDR2_BW_BY3_N	K28

QDR2_LB_BK17	AF31		QDR2_BW_BY4_N	AK33

QDR2_LB_BK19	K27		QDR2_BW_BY5_N	AK34

QDR2_LB_BK19	M28		QDR2_BW_BY6_N	AC29

QDR2_NC_A3	AG25		QDR2_BW_BY7_N	AD30

QDR2_NC_C6	AF24		QDR2_D_BY0_B0	T28

QDR2_R_N	AJ26		QDR2_D_BY0_B1	U30

QDR2_SA0	AJ29		QDR2_D_BY0_B2	R31

QDR2_SA1	AK29		QDR2_D_BY0_B3	T31

QDR2_SA10	AC28		QDR2_D_BY0_B4	N30

108	www.xilinx.com	Virtex-5 FPGA ML561 User Guide
		UG199 (v1.2) April 19, 2008

Image 108

Xilinx ML561 manual Fpga #3 Pinout, Table A-3FPGA #3 Pinout Signal Name Qdrii Memory Interface

Contents

Virtex-5 Fpga ML561 Memory Interfaces Development Board UG199 v1.2 April 19 Revision History Date Version Revision Table of Contents Electrical Requirements Appendix B Bill of Materials Appendix C LCD Interface Virtex-5 Fpga ML561 User Guide Guide Contents About This GuideAdditional Documentation Additional Support Resources Preface About This Guide Conventions TerminologyTypographical Online Document Virtex-5 Fpga ML561 User Guide Introduction About the Virtex-5 Fpga ML561 Memory Interfaces Tool Kit Virtex-5 Fpga ML561 Memory Interfaces Development Board Introduction Virtex-5 Fpga ML561 Memory Interfaces Development Board 2Virtex-5 Fpga ML561 Development Board Introduction Initial Board Check Before Applying Power Getting StartedDocumentation and Reference Design CD Applying Power to the Board Getting Started Hardware Description Hardware Overview 1ML561 XC5VLX50T-FFG1136 Board Placement Diagram Hardware Description Memories DDR400 Sdram ComponentsHardware Overview DDR2 Sdram Components Rldram II Devices Memory Details DDR400 and DDR2 Component MemoriesMemory Details DDR1RAS,CAS,WEN, DDR1CKE DDR2ODT10, DDR2RAS,CAS,WEN DDR2 Sdram Dimm DDR2DIMMRAS,CAS,WE,RESETN DimmDDR2DIMM15CNTLPAR DDR2DIMM15CNTLPARERR Qdrii and Rldram II Memories QDR2R,W,DLLOFFN External Interfaces RS-232Clocks MHz Lvpecl Clock SMA ClockMHz Clock DIP Switch User I/OsMHz System ACE Controller Oscillator GTP Clocks Seven-Segment Display Signal Mapping Seven-Segment DisplaysLight Emitting Diodes LEDs Pushbuttons Power On or Off Slide Switch Power Measurement HeaderSoft Touch Probe Points Liquid Crystal Display Connector Power Regulation Power DistributionPower Regulation Voltage Regulators 10PTH05010 Voltage Regulator 16Manual Voltage Margining Output Voltage Board Design Considerations Board Design Considerations 11ML561 Revision a PCB Stack-Up 19ML561 Revision a PCB Controlled Impedance TOP Power Consumption Electrical Requirements Total Available Power Power Consumed DDR400 Component InterfaceTotal Power Consumed Current Power Modules Capacity 2Power Planes Voltage Regulator Module VRM Part Electrical RequirementsStack-Up Power Consumption 3ML561 Power Plane CapacitiesCurrent Power Excess Device Description Quantity Power Consumed by Power Plane Electrical Requirements 3ML561 Power Plane Capacities Power Consumption 3ML561 Power Plane Capacities Current Power Excess Device DescriptionTotal Power Consumed 53.2 Fpga Internal Power Budget 4ML561 Fpga Power Estimate SummaryFpga #21 Signal Integrity Recommendations Termination and Transmission Line Summaries 2DDR2 Sdram Dimm Terminations Signal Fpga Driver 5RLDRAM II Terminations Signal HSTLI18HSTLIDCI18 HSTLIIDCI18 Signal Integrity Recommendations Configuration Configuration Modes Configuration 1Configuration Modes Jtag ChainJtag Port Parallel IV Cable Port System ACE Interface Configuration ML561 Hardware-Simulation Correlation Introduction Test Setup ML561 Hardware-Simulation Correlation Test Setup 1Single Trapezoid Eye Mask Definition Signal Integrity Correlation Results 2Two Triangular Eye Mask Definitions for VIH and VIL Signal Integrity Correlation Results DDR2 Component Write Operation2DDR2 Component Write Operation Correlation Results Measurement 3DIP12 Settings Description Voltage mV Voltage mV Time ns UG199c711071007 DDR2 Component Read Operation Fpga SSTL18IIDCII5DDR2 Component Read Operation Correlation Results Time ns UG199c715071107 UG199c717071007 UG199c719071007 DDR2 Dimm Write Operation DDR2 DIMM, 75 Ω ODT 8DIP12 Settings Description Noise Margin Overshoot / Undershoot Measurement UG199c722071107 UG199c724071107 UG199c726071007 UG199c729071007 DDR2 Dimm Read Operation 10DDR2 Dimm Read Operation Correlation Results DVW % UG199c731071107 1800.0 1600.0 1400.0 1200.0 1000.0 UG199c735071007 UG199c737071007 Qdrii Write Operation Fpga HSTLI1812 Qdrii Write Operation Correlation Results 800.0 600.0 400.0 200.0 000 Probe 3C7.1 at pin 1200.0 1600.0 UG199c742071107 UG199c744070907 3100.0 2600.0 2100.0 1600.0 1100.0 Qdrii Read Operation Fpga HSTLIDCI1814QDRII Read Operation Correlation Results UG199c749071107 1900.0 1700.0 1500.0 1300.0 1100.0 UG199c753070907 UG199c755070907 Summary and Recommendations Summary and RecommendationsNoise Margin Overshoot Operation 16Summary of Worst-Case SI Characteristics How to Generate a User-Specific Fpga Ibis Model How to Generate a User-Specific Fpga Ibis Model ML561 Hardware-Simulation Correlation Fpga Pinouts Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #1 Clock and Reset Signals FPGA2TOFPGA1MIITXCLK FPGA3TOFPGA1MIITXCLKFPGA2TOFPGA1MIITXDATA0 FPGA3TOFPGA1MIITXDATA0 Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #2 Pinout DDR2DIMM3CK2P DDR2DIMMDQBY0B4DDR2DIMM3CKE0 DDR2DIMMDQBY0B5 DDR2DIMMDQBY4B4 DDR2DIMMDQBY7B7DDR2DIMMDQBY4B5 DDR2DIMMDQCB07B0 DDR2DIMM5CS0N DDR2DIMMDQBY11B5 DDR2DIMM5CS1NDDR2DIMMDQBY11B6 DDR2DIMM5ODT0 AA9 DDR2DIMMDQBY11B7 Table A-2FPGA #2 Pinout Signal Name Fpga #2 Pinout Table A-2FPGA #2 Pinout Signal Name Fpga #2 Clock and Reset Signals FPGA2DIP0 FPGA2SOFTTOUCHBY1B7FPGA2DIP1 FPGA2SPYHOLEBK15 FPGA2TXN0BK120 FPGA2USBCTSN FPGA2TXN1BK120 FPGA2USBDSRNFPGA2TXP0BK120 FPGA2USBDTRN FPGA2TXP1BK120 FPGA2USBRSTN Table A-3FPGA #3 Pinout Signal Name Qdrii Memory Interface Fpga #3 Pinout QDR2DBY0B5 QDR2DBY4B1QDR2DBY0B6 QDR2DBY4B2 QDR2DBY7B6 QDR2QBY3B2QDR2DBY7B7 QDR2QBY3B3 QDR2QBY6B7 QDR2QBY7B4QDR2QBY6B8 QDR2QBY7B5 RLD2DBY0B5 RLD2DMBY23N RLD2DBY0B6 RLD2DQBY0B0 RLD2DBY0B7 RLD2DQBY0B1RLD2DBY0B8 RLD2DQBY0B2 RLD2DBY1B0 RLD2DQBY0B3 FPGA3RESETNIN RLD2DQBY3B4 RLD2DQBY3B7 RLD2DQBY3B5 RLD2DQBY3B8 RLD2DQBY3B6CLKTOFPGA3MGTN EXTCLKTOFPGA3N CLKTOFPGA3MGTP EXTCLKTOFPGA3P Table A-3FPGA #3 Pinout Signal Name Bill of Materials Table B-1Bill of Materials Appendix B Bill of Materials Table B-1Bill of Materials 4A LDO Virtex-5 Fpga ML561 User Guide 117 Appendix B Bill of Materials LCD Interface GeneralDisplay Hardware Design Hardware Schematic Diagram Table C-1Display Controller Specifications ParameterAppendix C LCD Interface Hardware Schematic Diagram Peripheral Device KS0713 64128EFCBC-XLP Block Diagram Controller Operation Table C-2 LCD Panel 124 Controller LCD Panel Connections Controller Power Supply Circuits Figure C-5Power Supply Circuits Operation Example of the 64128EFCBC-3LP Figure C-6LCD Controller Initialization Flow OFF Table C-4Resistor Value Settings Table C-5 Reference Voltage ParametersReference Voltage Parameter α Instruction Set Table C-6Display Instructions Hardware Schematic Diagram Table C-6Display Instructions Set page address Appendix C LCD Interface Table C-6Display Instructions EON Read/Write Characteristics 6800 Mode ERD LCD Panel Used in Full Graphics Mode Design Examples LCD Panel Used in Character Mode Display Command Byte Display Data Byte Figure C-10Block RAM Organization Figure C-11LCD Character Generator Controller Array Connector Numbering C D E F G H 140