Fpga #2 Pinout | Xilinx ML561 manual

Appendix A: FPGA Pinouts

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FPGA #2 Pinout

Table A-2lists the connections for FPGA #2 (U5).

Table A-2:FPGA #2 Pinout

Signal Name	Pin		Signal Name	Pin

	DDR2 DIMM Deep Interface

DDR2_DIMM_A0	AG30		DDR2_DIMM1_CK0_N	M26

DDR2_DIMM_A1	AH29		DDR2_DIMM1_CK0_P	M25

DDR2_DIMM_A10	AF31		DDR2_DIMM1_CK1_N	J25

DDR2_DIMM_A11	AC29		DDR2_DIMM1_CK1_P	J24

DDR2_DIMM_A12	AD30		DDR2_DIMM1_CK2_N	L26

DDR2_DIMM_A13	AA30		DDR2_DIMM1_CK2_P	L25

DDR2_DIMM_A14	AA29		DDR2_DIMM1_CKE0	G28

DDR2_DIMM_A15	AC30		DDR2_DIMM1_CKE1	H28

DDR2_DIMM_A2	AH30		DDR2_DIMM1_CS0_N	V27

DDR2_DIMM_A3	AJ30		DDR2_DIMM1_CS1_N	V28

DDR2_DIMM_A4	AF30		DDR2_DIMM1_ODT0	H24

DDR2_DIMM_A5	AF29		DDR2_DIMM1_ODT1	H25

DDR2_DIMM_A6	AK31		DDR2_DIMM2_CK0_N	AF26

DDR2_DIMM_A7	AJ31		DDR2_DIMM2_CK0_P	AF25

DDR2_DIMM_A8	AD29		DDR2_DIMM2_CK1_N	AG25

DDR2_DIMM_A9	AE29		DDR2_DIMM2_CK1_P	AF24

DDR2_DIMM_BA0	AB30		DDR2_DIMM2_CK2_N	AJ26

DDR2_DIMM_BA1	AA31		DDR2_DIMM2_CK2_P	AH27

DDR2_DIMM_BA2	AB31		DDR2_DIMM2_CKE0	AE24

DDR2_DIMM_CAS_N	V29		DDR2_DIMM2_CKE1	AD24

DDR2_DIMM_LB_BK11_IN	P32		DDR2_DIMM2_CS0_N	W27

DDR2_DIMM_LB_BK11_OUT	H33		DDR2_DIMM2_CS1_N	Y27

DDR2_DIMM_LB_BK13_IN	AJ32		DDR2_DIMM2_ODT0	AE26

DDR2_DIMM_LB_BK13_OUT	AK32		DDR2_DIMM2_ODT1	AE27

DDR2_DIMM_LB_BK15_IN	T28		DDR2_DIMM3_CK0_N	AA24

DDR2_DIMM_LB_BK15_OUT	T29		DDR2_DIMM3_CK0_P	Y24

DDR2_DIMM_RAS_N	Y28		DDR2_DIMM3_CK1_N	AC27

DDR2_DIMM_RESET_N	Y29		DDR2_DIMM3_CK1_P	AB27

DDR2_DIMM_WE_N	W29		DDR2_DIMM3_CK2_N	AA26

100	www.xilinx.com	Virtex-5 FPGA ML561 User Guide
		UG199 (v1.2) April 19, 2008

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Xilinx ML561 manual Fpga #2 Pinout

Contents

Virtex-5 Fpga ML561 Memory Interfaces Development Board UG199 v1.2 April 19 Revision History Date Version Revision Table of Contents Electrical Requirements Appendix B Bill of Materials Appendix C LCD Interface Virtex-5 Fpga ML561 User Guide About This Guide Guide ContentsAdditional Documentation Additional Support Resources Preface About This Guide Conventions TerminologyTypographical Online Document Virtex-5 Fpga ML561 User Guide Introduction About the Virtex-5 Fpga ML561 Memory Interfaces Tool Kit Virtex-5 Fpga ML561 Memory Interfaces Development Board Introduction Virtex-5 Fpga ML561 Memory Interfaces Development Board 2Virtex-5 Fpga ML561 Development Board Introduction Getting Started Initial Board Check Before Applying PowerDocumentation and Reference Design CD Applying Power to the Board Getting Started Hardware Description Hardware Overview 1ML561 XC5VLX50T-FFG1136 Board Placement Diagram Hardware Description DDR400 Sdram Components MemoriesHardware Overview DDR2 Sdram Components Rldram II Devices DDR400 and DDR2 Component Memories Memory DetailsMemory Details DDR1RAS,CAS,WEN, DDR1CKE DDR2ODT10, DDR2RAS,CAS,WEN DDR2 Sdram Dimm DDR2DIMMRAS,CAS,WE,RESETN DimmDDR2DIMM15CNTLPAR DDR2DIMM15CNTLPARERR Qdrii and Rldram II Memories QDR2R,W,DLLOFFN RS-232 External InterfacesClocks SMA Clock MHz Lvpecl ClockMHz Clock DIP Switch User I/OsMHz System ACE Controller Oscillator GTP Clocks Seven-Segment Display Signal Mapping Seven-Segment DisplaysLight Emitting Diodes LEDs Pushbuttons Power Measurement Header Power On or Off Slide SwitchSoft Touch Probe Points Liquid Crystal Display Connector Power Distribution Power RegulationPower Regulation Voltage Regulators 10PTH05010 Voltage Regulator 16Manual Voltage Margining Output Voltage Board Design Considerations Board Design Considerations 11ML561 Revision a PCB Stack-Up 19ML561 Revision a PCB Controlled Impedance TOP Power Consumption Electrical Requirements Total Available Power Power Consumed DDR400 Component InterfaceTotal Power Consumed Current Power Modules Capacity Electrical Requirements 2Power Planes Voltage Regulator Module VRM PartStack-Up Power Consumption 3ML561 Power Plane CapacitiesCurrent Power Excess Device Description Quantity Power Consumed by Power Plane Electrical Requirements 3ML561 Power Plane Capacities Current Power Excess Device Description Power Consumption 3ML561 Power Plane CapacitiesTotal Power Consumed 53.2 4ML561 Fpga Power Estimate Summary Fpga Internal Power BudgetFpga #21 Signal Integrity Recommendations Termination and Transmission Line Summaries 2DDR2 Sdram Dimm Terminations Signal Fpga Driver 5RLDRAM II Terminations Signal HSTLI18HSTLIDCI18 HSTLIIDCI18 Signal Integrity Recommendations Configuration Configuration Modes Configuration 1Configuration Modes Jtag ChainJtag Port Parallel IV Cable Port System ACE Interface Configuration ML561 Hardware-Simulation Correlation Introduction Test Setup ML561 Hardware-Simulation Correlation Test Setup 1Single Trapezoid Eye Mask Definition Signal Integrity Correlation Results 2Two Triangular Eye Mask Definitions for VIH and VIL Signal Integrity Correlation Results DDR2 Component Write Operation2DDR2 Component Write Operation Correlation Results Measurement 3DIP12 Settings Description Voltage mV Voltage mV Time ns UG199c711071007 Fpga SSTL18IIDCII DDR2 Component Read Operation5DDR2 Component Read Operation Correlation Results Time ns UG199c715071107 UG199c717071007 UG199c719071007 DDR2 Dimm Write Operation DDR2 DIMM, 75 Ω ODT 8DIP12 Settings Description Noise Margin Overshoot / Undershoot Measurement UG199c722071107 UG199c724071107 UG199c726071007 UG199c729071007 DDR2 Dimm Read Operation 10DDR2 Dimm Read Operation Correlation Results DVW % UG199c731071107 1800.0 1600.0 1400.0 1200.0 1000.0 UG199c735071007 UG199c737071007 Fpga HSTLI18 Qdrii Write Operation12 Qdrii Write Operation Correlation Results 800.0 600.0 400.0 200.0 000 Probe 3C7.1 at pin 1200.0 1600.0 UG199c742071107 UG199c744070907 3100.0 2600.0 2100.0 1600.0 1100.0 Fpga HSTLIDCI18 Qdrii Read Operation14QDRII Read Operation Correlation Results UG199c749071107 1900.0 1700.0 1500.0 1300.0 1100.0 UG199c753070907 UG199c755070907 Summary and Recommendations Summary and RecommendationsNoise Margin Overshoot Operation 16Summary of Worst-Case SI Characteristics How to Generate a User-Specific Fpga Ibis Model How to Generate a User-Specific Fpga Ibis Model ML561 Hardware-Simulation Correlation Fpga Pinouts Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #1 Clock and Reset Signals FPGA2TOFPGA1MIITXCLK FPGA3TOFPGA1MIITXCLKFPGA2TOFPGA1MIITXDATA0 FPGA3TOFPGA1MIITXDATA0 Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #2 Pinout DDR2DIMM3CK2P DDR2DIMMDQBY0B4DDR2DIMM3CKE0 DDR2DIMMDQBY0B5 DDR2DIMMDQBY4B4 DDR2DIMMDQBY7B7DDR2DIMMDQBY4B5 DDR2DIMMDQCB07B0 DDR2DIMM5CS0N DDR2DIMMDQBY11B5 DDR2DIMM5CS1NDDR2DIMMDQBY11B6 DDR2DIMM5ODT0 AA9 DDR2DIMMDQBY11B7 Table A-2FPGA #2 Pinout Signal Name Fpga #2 Pinout Table A-2FPGA #2 Pinout Signal Name Fpga #2 Clock and Reset Signals FPGA2DIP0 FPGA2SOFTTOUCHBY1B7FPGA2DIP1 FPGA2SPYHOLEBK15 FPGA2TXN0BK120 FPGA2USBCTSN FPGA2TXN1BK120 FPGA2USBDSRNFPGA2TXP0BK120 FPGA2USBDTRN FPGA2TXP1BK120 FPGA2USBRSTN Table A-3FPGA #3 Pinout Signal Name Qdrii Memory Interface Fpga #3 Pinout QDR2DBY0B5 QDR2DBY4B1QDR2DBY0B6 QDR2DBY4B2 QDR2DBY7B6 QDR2QBY3B2QDR2DBY7B7 QDR2QBY3B3 QDR2QBY6B7 QDR2QBY7B4QDR2QBY6B8 QDR2QBY7B5 RLD2DBY0B5 RLD2DMBY23N RLD2DBY0B6 RLD2DQBY0B0 RLD2DBY0B7 RLD2DQBY0B1RLD2DBY0B8 RLD2DQBY0B2 RLD2DBY1B0 RLD2DQBY0B3 FPGA3RESETNIN RLD2DQBY3B4 RLD2DQBY3B7 RLD2DQBY3B5 RLD2DQBY3B8 RLD2DQBY3B6CLKTOFPGA3MGTN EXTCLKTOFPGA3N CLKTOFPGA3MGTP EXTCLKTOFPGA3P Table A-3FPGA #3 Pinout Signal Name Bill of Materials Table B-1Bill of Materials Appendix B Bill of Materials Table B-1Bill of Materials 4A LDO Virtex-5 Fpga ML561 User Guide 117 Appendix B Bill of Materials General LCD InterfaceDisplay Hardware Design Table C-1Display Controller Specifications Parameter Hardware Schematic DiagramAppendix C LCD Interface Hardware Schematic Diagram Peripheral Device KS0713 64128EFCBC-XLP Block Diagram Controller Operation Table C-2 LCD Panel 124 Controller LCD Panel Connections Controller Power Supply Circuits Figure C-5Power Supply Circuits Operation Example of the 64128EFCBC-3LP Figure C-6LCD Controller Initialization Flow OFF Table C-5 Reference Voltage Parameters Table C-4Resistor Value SettingsReference Voltage Parameter α Instruction Set Table C-6Display Instructions Hardware Schematic Diagram Table C-6Display Instructions Set page address Appendix C LCD Interface Table C-6Display Instructions EON Read/Write Characteristics 6800 Mode ERD LCD Panel Used in Full Graphics Mode Design Examples LCD Panel Used in Character Mode Display Command Byte Display Data Byte Figure C-10Block RAM Organization Figure C-11LCD Character Generator Controller Array Connector Numbering C D E F G H 140